Abstract: A supply-voltage detecting stage (11) that supplies first and second reference currents (I.sub.REFP and I.sub.REFN) which vary with the supply voltage (V.sub.cc) and are coupled by first and second gain stages (12A and 12B), respectively, to first and second temperature-detecting stages (13A and 13B), respectively. First and second temperature-detecting stages (13A and 13B) increase the coupled reference currents (I.sub.REFP and I.sub.REFN), respectively, to compensate for temperature increase through use temperature-sensitive, long-channel transistors (M34-M37 and M42-M45), supplying temperature and supply-voltage compensated output bias voltages at output terminals (MIRN and MIRP).

Abstract: The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

Abstract: In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate coupled to a wordline and each memory cell of a row in another sector has a control gate coupled to that wordline, a method for programming a memory cell in one sector of said method includes connecting at least the second common array-source line to each bitline coupled to drains of columns of memory cells in the another sector, then biasing at a positive voltage both the common array-source line and the bitlines coupled to drains of memory cells in columns of the another sector, and then applying a programming voltage to the selected wordline coupled to the control gate of the selected cell in the first sector.

Abstract: Low-voltage-correcting bias circuitry for a sense amplifier includes first, second and third N-channel transistors. The channel of the first transistor couples a current mirror to the input terminal of the amplifier and the gate of the second transistor, the channel of the second transistor couples the gate of the first transistor to a reference terminal. The channel of the third transistor couples the supply voltage to the gate of the first transistor. The gate of the third transistor is coupled to a reference voltage. A P-channel transistor has a channel coupling the supply voltage to the gate of the first transistor. The gate of the P-channel transistor is coupled to a low-voltage-sensing signal. Pre-charge circuitry includes a nonvolatile memory cell and fourth, fifth and sixth N-channel transistors. The channel of the fourth transistor is in series with the channel of the memory cell. The channel of the fifth transistor couples the channel of the memory cell to the input of the sense amplifier.

Abstract: A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.) are simultaneously checked one row at a time and one column position at a time, to see whether or not any cell (10) is over-erased. If, at any time during the procedure a cell (10) is found to be over-erased, the over-erased condition is corrected and the erase procedure continues, but with erase pulses applied only to those subarrays (S1, S2, etc.) having non-erased memory cells (10) as in prior-art subarray erase procedures. Under almost all circumstances, the procedure of this invention decreases over-all erase time.

Abstract: A fault sensing circuit for detecting the state of at least one latch controlled by at least one control signal is provided. The circuit comprises an additional latch also controlled by the same control signal and receiving an input of a known value. The output of the additional latch is coupled to an I/O pin where an external circuit may monitor its logic state to determine the occurrence of a fault.

Abstract: A virtual ground memory includes an array of rows and columns of memory cells and a plurality of alternating first and second column lines. The cells in each column are coupled to a first column line and a second column line. A first decoder selects a plurality of first column lines in response to first decoded address signals and selects one of the selected plurality of first column lines in response to second decoded address signals.

Abstract: The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.

Abstract: An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging.

Abstract: The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.

Abstract: The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.

Abstract: The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.

Abstract: A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

Abstract: A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded.

Abstract: The indicator circuit and method of this invention include an OR circuit having at least two inputs and an output. A signature mode signal input is connected to one input of the OR circuit and a special test mode signal input is connected to a second input of the OR circuit. A logic circuit for providing indicator signals has at least three inputs and at least two outputs. A first input to the logic circuit is connected to the output of the OR circuit. At least one signature address signal is connected to a second input of the logic circuit. The signal indicating the results of the special test mode is connected to a third input of the logic circuit. A first preprogrammed code indicator circuit has an input connected to a first output of the logic circuit and a second preprogrammed code indicator has an input connected to a second output of the logic circuit. The first preprogrammed code indicator may contain, for example, a manufacturer code.

Abstract: A common connection to reduces the amount of chip area required to perform read and programming functions, particularly where signals such as read, programming, supply voltage and data signals are generated from remote locations on the memory chip. The common connection is made in an integrated circuit having a control circuit, a plurality of memory cell arrays having column lines, a sense amplifier circuit, and a programming circuit including at least first and second parts. At least one column of one memory cell array is selectively connected to a common line/node upon receiving at least a first signal from the control circuit. The first part of the programming circuit is selectively connected to the common line/node upon receiving a second signal from the control circuit. The second part of the programming circuit is connected to the common line/node upon receiving a third signal from the control circuit.

Abstract: A circuit and method for rapid removal of drain-column programming voltages from drain-column lines of a memory array. The circuit includes a resistor/transistor connected between a supply voltage and a common node, the resistor/transistor being enabled by a program enable signal. During the discharge operation, the source-drain paths of a driver transistors of the array connect column lines to reference potential. The gates of the driver transistors are coupled to the common node. An enabling transistor has a source-drain path connecting reference potential to the common node and has a gate connected to the program enable signal. The circuit includes at least one inverter, an OR circuit, and a bypass transistor. The bypass transistor has a source-drain path connected between the supply voltage and the common node and a gate coupled to the common node through the inverter and the OR circuit.

Abstract: A switching circuit for selectively coupling a first power supply to a power bus includes a first input terminal for connection to the first power supply and a means for coupling said first input terminal to a first node. A first transistor has a first source/drain region coupled to the first node and a second source/drain region coupled to the power bus. The first transistor is on in response to a first control signal applied to its gate to couple the first node to the power bus. A bias circuit is coupled to the substrate of the first transistor to prevent forward biasing of a junction between its substrate and its second source/drain region when the first transistor is on.

Abstract: Apparatus for determining the field position (00, 01, 10, 11) of an integrated circuit (18) within a reticle area (12) which contains a plurality of such integrated circuits (14-20) includes a plurality of memory cells (76, 80) formed within the integrated circuit (18) for encoding the field position. Circuitry (40, 94, 100, 104, 106) is provided for reading the states of the memory cells to ascertain the field position.

Abstract: A test circuit for determining whether or not fuse-links of an integrated circuit have been opened or closed properly by, for example, a laser device. The test circuit of this invention, in one embodiment, includes a variable impedance, such as a P-channel transistor, connected between a voltage source and an output terminal, the impedance having one value with a first input applied to the variable impedance control terminal and having a second, larger value in response to a second input applied to the variable impedance control terminal. At least one programmable fuse-link and a gate are connected in series between the output terminal and a source of reference potential. A means for providing control inputs to the variable impedance is connected between a test mode input signal and the control terminal of the variable impedance. The means for providing control inputs to the P-channel transistor may include a second, current-mirror-connected P-channel transistor.