Abstract: A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline.

Abstract: A method for measuring the access time or speed of PROM devices is described. The PROM (10) includes a matrix of erased memory cells (30-70) each selectable by an address, and readable by a sense amplifier (112). The method comprises providing an invalid address and reading the level at the sense amplifier (112). A valid address is then provided, and the memory cell addressed is read. The above steps are repeated until all memory cells are read. In this manner, the time required to access an erased memory cell after accessing a programmed memory cell, as simulated by a nonexistent memory cell, may be measured.

Abstract: Apparatus for decoding a plurality of electrically programmable memory cells (30-70) comprises an array source driver circuit (72) for selectively connecting a first terminal (140) of a selected memory cell (152) to a program bias voltage or to ground. A bit line driver circuit (94-100, 120) selectively connects a second terminal (154) of said selected memory cell (152) to ground or to a read sense node (115). Reading is performed by connecting the first terminal (140) to ground and the second terminal (154) to the read sense node (115). Programming is performed by connecting the first terminal (140) to the program bias voltage and the second terminal (154) to ground.