Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

Abstract: A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

Abstract: A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.

Abstract: A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

Abstract: A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.

Abstract: A complementary metal oxide semiconductor (CMOS) fabrication process. The process comprises creating a polysilicon layer having a first thickness for a transistor gate area and a second thickness for a fuse area. The first thickness is greater than the second thickness, wherein most of the polysilicon in the fuse area will react with a metal layer to form polysilicide during a rapid thermal anneal (RTA) process.

Abstract: A silicon-on-insulator semiconductor device, including a silicon-on-insulator wafer having a silicon active layer, a dielectric isolation layer a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate, in which the at least one isolation trench includes a layer of a passivating insulator in a lower portion of the isolation trench and in contact with the dielectric insulation layer. The passivating insulator prevents formation of a bird's beak between the silicon active layer and the dielectric insulation layer during subsequent fabrication of the isolation trench.

Abstract: Gate oxide surface irregularities, such as surface roughness, are reduced by treatment with an oxygen-containing plasma. Embodiments include forming a gate oxide layer and then treating the formed gate oxide layer with an oxygen plasma to repair weak spots and fill in pin holes and surface irregularities, thereby reducing gate/gate oxide interface roughness.

Abstract: An entirely aqueous method for concentrating beta-glucan from a beta-glucan source, such as milled cereal bran, grain or distiller's dried grain. The method comprises providing an alkaline aqueous extract of a beta-glucan source; acidifying or neutralizing the extract and heating the extract to between about 60° C. and 100° C.; cooling the extract, whereby a flocculate is formed; acidifying the cooled extract if the extract was neutralized; and removing the flocculate from the aqueous solution to form an intermediate solution. The intermediate solution may be subjected to ultrafiltration for further purification of beta-glucan, or may be evaporated, resulting in formation of a solid film enriched in beta-glucan. Beta-glucan has cholesterol-lowering properties and is a topical immunostimulant.

Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.

Abstract: A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at least a portion of the layer of conductive material is removed according to the mask.

Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.

Abstract: An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric layer over the patterned amorphous carbon layer, removing a portion of the deposited dielectric layer to expose a top of the patterned amorphous carbon layer, removing the patterned amorphous carbon layer leaving an aperture in the dielectric layer, and forming a metal gate in the aperture of the dielectric layer.

Abstract: An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a field area and portions of an amorphous carbon layer located in an active area. Portions of the amorphous carbon layer are polished down to a hard polish stop layer. The method can also include ashing away residual amorphous carbon from the amorphous carbon layer.

Abstract: Apparatus for heat treating a cutting tool comprises a furnace and a tool holder within the furnace adapted to receive therein a first portion of the tool, a second portion of the tool projecting from the tool holder, the second portion of the tool being directly exposed to radiant heat from at least one radiant heating element within the furnace with the first portion of the tool being shielded from the radiant heat.

Abstract: An entirely aqueous method for concentrating beta-glucan from a beta-glucan source, such as milled cereal bran, grain or distiller's dried grain. The method comprises providing an alkaline aqueous extract of a beta-glucan source; acidifying or neutralizing the extract and heating the extract to between about 60° C. and 100° C.; cooling the extract, whereby a flocculate is formed; acidifying the cooled extract if the extract was neutralized; and removing the flocculate from the aqueous solution to form an intermediate solution. The intermediate solution may be subjected to ultrafiltration for further purification of beta-glucan, or may be evaporated, resulting in formation of a solid film enriched in beta-glucan. Beta-glucan has cholesterol-lowering properties and is a topical immunostimulant.