Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

Abstract: An apparatus for drying bulk material can include a housing defining a chamber, an inlet for receiving the bulk material into the chamber, and an outlet for discharging the bulk material from the chamber. At least one conveyor mechanism can be disposed within the housing and can be arranged to convey the bulk material from the inlet to the outlet. A ventilation system can be coupled to the chamber and configured to remove water vapor from the chamber. A method of drying bulk material can include receiving the bulk material into a chamber, conveying the bulk material within the chamber, removing water vapor from the chamber, and discharging the bulk material from the chamber. The system can be used to process peat moss or other bulk materials, such as soil, manure, wood pulp, vegetables, or other products.

Abstract: SRAM memory including: a matrix of memory cells; bit lines and word lines; read ports associated with the memory cells and coupled to the bit lines and to the word lines; local virtual ground, LVGND, lines each coupled to the reference potential terminals of the read ports of at least one row of memory cells; local control elements each configured to electrically couple one of the LVGND lines to a power supply potential or to a global virtual ground line, or GVGND line; a global control element configured to couple the GVGND line to the power supply electric potential or to a reference electric potential.

Abstract: A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.

Abstract: A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M?1, are coupled together.

Abstract: A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

Abstract: A 3D-RAM memory comprising: several memory cell arrays distributed in several superimposed memory layers; a word line driver; a row decoder coupled to the word line driver; wherein the row decoder and the word line driver are arranged in a layer of command electronics which is separate from the memory layers, and wherein, in each of the memory layers, each of the word lines is connected to an output of an electronic selection device arranged in the memory layer, a data input of which is connected to the word line driver, a command input of which is connected to the row decoder, and which is configured to let a signal of access to the transistors pass or not depending on the value of a received command signal.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.

Abstract: SRAM memory including: a matrix of memory cells; bit lines and word lines; read ports associated with the memory cells and coupled to the bit lines and to the word lines; local virtual ground, LVGND, lines each coupled to the reference potential terminals of the read ports of at least one row of memory cells; local control elements each configured to electrically couple one of the LVGND lines to a power supply potential or to a global virtual ground line, or GVGND line; a global control element configured to couple the GVGND line to the power supply electric potential or to a reference electric potential.

Abstract: A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

Abstract: A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.

Abstract: A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M?1, are coupled together.

Abstract: Static random access memory device comprising a memory matrix provided with at least one column (COL1) formed from a plurality of SRAM memory cells (C11, CN1), the device being provided with a fast erase memory circuit configured to connect a first bit line (BLT) and a second bit line (BLF) shared by cells in said column, following reception of an erase signal (ERASE).

Abstract: An apparatus includes a top portion and a middle portion. The top portion includes an inlet for receiving peat moss. A feeding mechanism delivers the peat moss from the top portion to the middle portion. A compression mechanism housed in the middle portion includes at least one roller assembly for at least partially dewatering the peat moss. The roller assembly can include upper and lower rollers. Peat moss passing between the rollers can be pressed to reduce moisture content of the peat moss. The lower roller can include perforations allowing moisture to drain away from the peat moss. Speeds of rotation of the rollers and/or a distance between the rollers can be adjustable. A bottom portion underneath the middle portion can include an outlet for discharging the peat moss.

Abstract: A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.

Abstract: A SRAM cell, including, in a stack of layers, transistors including at least first and second access transistors connected to a word line, the first access transistor coupling a first bit line and a first storage node and the second access transistor coupling a second bit line and a second storage node, and a flip-flop including a first conduction transistor coupling the first storage node to a source of a first reference potential and having its gate coupled to the second storage node and a second conduction transistor coupling the second storage node to the source of the first reference potential and having its gate coupled to the first storage node.

Abstract: A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.

Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.