Patents by Inventor Philippe Noel
Philippe Noel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170345505Abstract: A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.Type: ApplicationFiled: May 23, 2017Publication date: November 30, 2017Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Philippe Noel, Kaya Can Akyel
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Publication number: 20170316825Abstract: A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.Type: ApplicationFiled: April 13, 2017Publication date: November 2, 2017Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Bastien Giraud, Alexandre Levisse, Jean-Philippe Noel
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Patent number: 9479168Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: GrantFiled: March 26, 2014Date of Patent: October 25, 2016Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
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Publication number: 20150287722Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.Type: ApplicationFiled: October 11, 2013Publication date: October 8, 2015Inventors: Bastien Giraud, Philippe Flatresse, Jean-Philippe Noel, Bertrand Pelloux-Prayer
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Patent number: 9136366Abstract: An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.Type: GrantFiled: January 16, 2014Date of Patent: September 15, 2015Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics SAInventors: Bastien Giraud, Jean-Philippe Noel, Maud Vinet
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Patent number: 9092590Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.Type: GrantFiled: December 13, 2013Date of Patent: July 28, 2015Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics SAInventors: Bastien Giraud, Philippe Flatresse, Matthieu Le Boulaire, Jean-Philippe Noel
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Patent number: 9093499Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.Type: GrantFiled: September 26, 2012Date of Patent: July 28, 2015Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
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Patent number: 9000840Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.Type: GrantFiled: December 19, 2013Date of Patent: April 7, 2015Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroeletronics SA, STMicroeletronics (Crolles 2) SASInventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel
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Patent number: 8969967Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.Type: GrantFiled: May 22, 2012Date of Patent: March 3, 2015Assignee: Commissariat a l'energie et aux energies alternativesInventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
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Patent number: 8937505Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.Type: GrantFiled: December 19, 2013Date of Patent: January 20, 2015Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Yvain Thonnart
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Patent number: 8870520Abstract: A method for unlatching a latch on a container includes providing a lifting arm for lifting a latched container. Moving the latched container from a first position to a second position with the lifting arm and unlatching the container by flexing the latch on the container by moving the container from the first position to the second position. The latch includes a first member which is pivotably mounted to a lid. A second member is adapted to selectively engage a projection on a body of the container. An arch member connects the first member to the second member and a handle extends in the direction opposite to the direction in which the arch member extends. The step of deflecting the handle is by movement of the moving member to the flex the latch.Type: GrantFiled: March 28, 2011Date of Patent: October 28, 2014Assignee: IPL, Inc.Inventors: Louis Mercier, Roch Nolet, Philippe Noel, Marc Talbot-Pouliot, Michel Fillion, Serge Gingras, Jean-Sebastien Guilmette
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Publication number: 20140292374Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: ApplicationFiled: March 26, 2014Publication date: October 2, 2014Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
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Publication number: 20140231916Abstract: An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.Type: ApplicationFiled: January 16, 2014Publication date: August 21, 2014Inventors: Bastien Giraud, Jean-Philippe Noel, Maud Vinet
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Publication number: 20140176216Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).Type: ApplicationFiled: December 19, 2013Publication date: June 26, 2014Inventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel
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Publication number: 20140176228Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.Type: ApplicationFiled: December 19, 2013Publication date: June 26, 2014Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Yvain Thonnart
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Publication number: 20140173544Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.Type: ApplicationFiled: December 13, 2013Publication date: June 19, 2014Inventors: Bastien Giraud, Philippe Flatresse, Matthieu Le Boulaire, Jean-Philippe Noel
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Patent number: 8723267Abstract: The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.Type: GrantFiled: April 1, 2010Date of Patent: May 13, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Olivier Thomas, Jean-Philippe Noel
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Publication number: 20140077300Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.Type: ApplicationFiled: May 22, 2012Publication date: March 20, 2014Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
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Publication number: 20130333253Abstract: A peat moss harvesting apparatus includes a supporting structure attachable to a carrier vehicle, and a conveyor mechanism mounted to the supporting structure. The conveyor mechanism includes first and second pulleys and a belt assembly. The belt assembly includes at least one flexible drive element, a plurality of transverse supports mounted to the drive element, and a plurality of cover members mounted to the transverse supports. The cover members define a support surface for conveying material. The transverse supports may be longitudinally spaced apart from one another along the drive element. Each of the cover members may be fixed to a respective one of the transverse supports.Type: ApplicationFiled: June 19, 2013Publication date: December 19, 2013Inventor: Philippe Noël
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Patent number: 8482070Abstract: An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.Type: GrantFiled: August 1, 2012Date of Patent: July 9, 2013Assignee: STMicroelectronics (Crolles 2)Inventors: Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Matthieu Le Boulaire