Patents by Inventor Pierre M. Petroff
Pierre M. Petroff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8227825Abstract: A high efficiency light emitting diode (LED) comprised of a substrate, a buffer layer grown on the substrate (if such a layer is needed), a first active region comprising primary emitting species (PES) that are electrically-injected, a second active region comprising secondary emitting species (SES) that are optically-pumped by the light emitted from the PES, and photonic crystals, wherein the photonic crystals act as diffraction gratings to provide high light extraction efficiency, to provide efficient excitation of the SES, and/or to modulate the far-field emission pattern.Type: GrantFiled: July 28, 2010Date of Patent: July 24, 2012Assignee: The Regents of the University of CaliforniaInventors: Frederic S. Diana, Aurelien J. F. David, Pierre M. Petroff, Claude C. A. Weisbuch
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Publication number: 20110291130Abstract: A high efficiency light emitting diode (LED) comprised of a substrate, a buffer layer grown on the substrate (if such a layer is needed), a first active region comprising primary emitting species (PES) that are electrically-injected, a second active region comprising secondary emitting species (SES) that are optically-pumped by the light emitted from the PES, and photonic crystals, wherein the photonic crystals act as diffraction gratings to provide high light extraction efficiency, to provide efficient excitation of the SES, and/or to modulate the far-field emission pattern.Type: ApplicationFiled: August 1, 2011Publication date: December 1, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Frédéric S. Diana, Aurélien J. F. David, Pierre M. Petroff, Claudr C.A. Weisbuch
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Patent number: 7906775Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.Type: GrantFiled: December 4, 2006Date of Patent: March 15, 2011Assignee: California Institute of TechnologyInventors: James R. Heath, Pierre M. Petroff, Nicholas A. Melosh
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Publication number: 20100327305Abstract: A high efficiency light emitting diode (LED) comprised of a substrate, a buffer layer grown on the substrate (if such a layer is needed), a first active region comprising primary emitting species (PES) that are electrically-injected, a second active region comprising secondary emitting species (SES) that are optically-pumped by the light emitted from the PES, and photonic crystals, wherein the photonic crystals act as diffraction gratings to provide high light extraction efficiency, to provide efficient excitation of the SES, and/or to modulate the far-field emission pattern.Type: ApplicationFiled: July 28, 2010Publication date: December 30, 2010Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Frédéric S. Diana, Aurélien J.F. David, Pierre M. Petroff, Claude C.A. Weisbuch
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Publication number: 20100258785Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.Type: ApplicationFiled: December 4, 2006Publication date: October 14, 2010Applicant: California Institute of TechnologyInventors: James R. Heath, Pierre M. Petroff, Nicholas A. Melosh
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Patent number: 7768023Abstract: A high efficiency light emitting diode (LED) comprised of a substrate, a buffer layer grown on the substrate (if such a layer is needed), a first active region comprising primary emitting species (PES) that are electrically-injected, a second active region comprising secondary emitting species (SES) that are optically-pumped by the light emitted from the PES, and photonic crystals, wherein the photonic crystals act as diffraction gratings to provide high light extraction efficiency, to provide efficient excitation of the SES, and/or to modulate the far-field emission pattern.Type: GrantFiled: October 14, 2005Date of Patent: August 3, 2010Assignee: The Regents of the University of CaliforniaInventors: Frédéric S. Diana, Aurélien J. F. David, Pierre M. Petroff, Claude C. A. Weisbuch
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Patent number: 7470954Abstract: A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and are self-assembled onto the photoresist nanopatterns. The nanoparticles are selectively positioned in the holes due to the capillary forces related to the pattern geometry, with a controllable number of particles per lattice point.Type: GrantFiled: November 14, 2005Date of Patent: December 30, 2008Assignee: The Regents of the University of CaliforniaInventors: Seung-Heon Lee, Frédéric S. Diana, Antonio Badolato, Pierre M. Petroff, Edward J. Kramer
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Patent number: 7161168Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.Type: GrantFiled: July 28, 2003Date of Patent: January 9, 2007Assignee: The Regents of the University of CaliforniaInventors: James R. Heath, Pierre M. Petroff, Nicholas A. Melosh
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Patent number: 6989324Abstract: A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and are self-assembled onto the photoresist nanopatterns. The nanoparticles are selectively positioned in the holes due to the capillary forces related to the pattern geometry, with a controllable number of particles per lattice point.Type: GrantFiled: January 15, 2004Date of Patent: January 24, 2006Assignee: The Regents of the University of CaliforniaInventors: Seung-Heon Lee, Frédéric S. Diana, Antonio Badolato, Pierre M. Petroff, Edward J. Kramer
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Patent number: 6583436Abstract: A method for growing strain-engineered, self-assembled, semiconductor quantum dots (QDs) into ordered lattices. The nucleation and positioning of QDs into lattices is achieved using a periodic sub-surface lattice built-up on a substrate, stressor layer, and spacer layer. The unit cell dimensions, orientation and the number of QDs in the basis are tunable. Moreover, a 2D lattice can be replicated at periodic intervals along the growth direction to form a three-dimensional (3D) lattice of QDs.Type: GrantFiled: June 27, 2001Date of Patent: June 24, 2003Assignee: The Regents of the University of CaliforniaInventors: Pierre M. Petroff, James S. Speck, Jo Anna Johnson, Hao Lee
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Patent number: 6541788Abstract: A method and device for converting light from a first wavelength to a second wavelength. The method comprises the steps of exciting an electron in a quantum dot with an incident infrared photon having the first wavelength, the excited electron having a first energy, tunneling the excited electron through a barrier into a stress induced quantum dot, and recombining the excited electron with a hole in the stress induced quantum dot, therein producing a photon having the second wavelength, typically in the visible range.Type: GrantFiled: October 27, 1999Date of Patent: April 1, 2003Assignee: The Regents of the University of CaliforniaInventors: Pierre M. Petroff, Naoto Horiguchi
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Publication number: 20020162995Abstract: A method and device for converting light from a first wavelength to a second wavelength. The method comprises the steps of exciting an electron in a quantum dot with an incident infrared photon having the first wavelength, the excited electron having a first energy, tunneling the excited electron through a barrier into a stress induced quantum dot, and recombining the excited electron with a hole in the stress induced quantum dot, therein producing a photon having the second wavelength, typically in the visible range.Type: ApplicationFiled: October 27, 1999Publication date: November 7, 2002Inventors: PIERRE M. PETROFF, NAOTO NMI HORIGUCHI
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Publication number: 20020074543Abstract: A method for growing strain-engineered, self-assembled, semiconductor quantum dots (QDs) into ordered lattices. The nucleation and positioning of QDs into lattices is achieved using a periodic sub-surface lattice built-up on a substrate, stressor layer, and spacer layer. The unit cell dimensions, orientation and the number of QDs in the basis are tunable. Moreover, a 2D lattice can be replicated at periodic intervals along the growth direction to form a three-dimensional (3D) lattice of QDs.Type: ApplicationFiled: June 27, 2001Publication date: June 20, 2002Inventors: Pierre M. Petroff, James S. Speck, Jo Anna Johnson, Hao Lee
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Patent number: 6307241Abstract: Submicron ferromagnets, of selected size and spacing, are introduced into semiconductor by means of ion implantation and subsequent heat treatments. The resulting semiconductor contains ferromagnets at high density and which exhibit Curie temperatures exceeding room temperature. The semiconductor retains its intrinsic physical properties, such as optical and transport properties, after incorporation of the ferromagnetic nanostructures.Type: GrantFiled: June 7, 1995Date of Patent: October 23, 2001Assignee: The Regents of the Unversity of CaliforniaInventors: David D. Awschalom, Pierre M. Petroff, Jing Shi, James M. Kikkawa
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Patent number: 5192709Abstract: A method for modulation doping of semiconductor heterostructures includes forming a semiconductor heterostructure comprising a substrate layer, a narrow band-gap quantum well layer, and a donor implantation layer. A focused ion beam writes across the surface of the donor implantation layer, at a maximum angle of incident less than that of the channeling half-angle .alpha. of the donor implantation layer. Channeled dopant ions penetrate deep within the donor implantation layer, far from surface damage sites, and away from the quantum well layer. The addition of a dechanneling layer within the donor implantation layer, and of a series of spacer layers, further localizes the implanted donor ions and separates these ions from the quantum well layer. Once activated by a thermal annealing process, the donor ions release carriers into the quantum well layer where carrier mobility is unimpeded by donor ion collisions. An alternative embodiment implants the donor ions before the heterostructure is completely formed.Type: GrantFiled: September 17, 1991Date of Patent: March 9, 1993Assignee: University of California Office of Technology TransferInventor: Pierre M. Petroff
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Patent number: 5013683Abstract: A method for growing a superlattice structure on a substrate. First, a periodic array of monoatomic surface steps are created on the surface of the substrate at an area to have the superlattice structure grown thereon. There is apparatus for creating a beam of a material being input thereto and for selectively including or not including respective ones of a plurality of materials within the beam. The beam is directed at the steps of the substrate. Finally, logic causes control apparatus to include and not include respective ones of the materials within the beam in a pre-established pattern of time periods which will cause the materials to be deposited on the steps in a series of stacked monolayers. Tilted Superlattices (TSLs) and Coherent Tilted Superlattices (CTSLs) are created. The method can create pseudo ternary semiconductor alloys as part of a CTSL by employing at least two binary compound semiconductor alloys in the deposition process.Type: GrantFiled: January 23, 1989Date of Patent: May 7, 1991Assignee: The Regents of the University of CaliforniaInventors: Pierre M. Petroff, Herbert Kroemer
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Patent number: 4860068Abstract: Single GaAs quantum well or single GaAs active layer or single reverse interface structures with Al.sub.x Ga.sub.1-x As barrier layers have improved qualities when one or more narrow bandgap GaAs getter-smoothing layers, which are thin, are grown and are incorporated in the barrier layer before and in close proximity to the active layer.Type: GrantFiled: January 27, 1988Date of Patent: August 22, 1989Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: Arthur C. Gossard, Robert C. Miller, Pierre M. Petroff
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Patent number: 4794440Abstract: A heterojunction bipolar transistor having means for changing carrier transport properties is described.Type: GrantFiled: December 30, 1987Date of Patent: December 27, 1988Assignee: American Telephone and Telegraph Company, AT&T Bell laboratoriesInventors: Federico Capasso, Arthur C. Gossard, John R. Hayes, Roger J. Malik, Pierre M. Petroff
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Patent number: 4751194Abstract: A method of fabricating quantum well wires and boxes is described in which interdiffusion in a semiconductor having a compositional profile is enhanced by the presence of defects created by ion implantation in localized regions.Type: GrantFiled: June 27, 1986Date of Patent: June 14, 1988Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: Joel B. Cibert, Arthur C. Gossard, Stephen J. Pearton, Pierre M. Petroff
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Patent number: 4591889Abstract: Semiconductor devices having submonolayer superlattices are described. These devices may have periodic compositional variations in a direction parallel to the substrate surface as well as in the perpendicular direction. Such superlattices are useful in numerous types of devices including lasers, transistors, etc.Type: GrantFiled: September 14, 1984Date of Patent: May 27, 1986Assignee: AT&T Bell LaboratoriesInventors: Arthur C. Gossard, Pierre M. Petroff