Abstract: The present invention is related to a display device, including: a plurality of sub-pixel areas, each including a pixel circuit, each pixel circuit including: a diode, configured to be in a forward-biasing state during a display phase of the pixel circuit for light-emitting and configured to be in a reverse-biasing state in a sensing phase of the pixel circuit for light-sensing; a driving transistor for driving the diode during the display phase and serving as a source follower in the sensing phase; first to sixth transistors, applied to the gates of the first to sixth transistors respectively so that the pixel circuit switching between the display phase and the sensing phase; and a capacitor for storing a data voltage to be written to the diode in the display phase and storing the charge accumulated by the diode in the sensing phase.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.

Abstract: The present invention is related to a display device, including: a plurality of sub-pixel areas, each including a pixel circuit, each pixel circuit including: a diode, configured to be in a forward-biasing state during a displaying phase of the pixel circuit for emitting light and configured to be in a reverse-biasing state in a sensing phase of the pixel circuit so as to generate a sensing voltage; a first circuit by applying gate control signals to each pixel circuit, so that each pixel circuit switches between the display phase and the sensing phase, respectively; and a second circuit including a plurality of readout circuits, each readout circuit includes an operational amplifier for reading out the sensing voltage in the sensing phase.

Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

Abstract: The present invention is related to a display device, including: a display panel having a plurality of sub-pixel areas, each including a pixel circuit, each pixel circuit including: a diode, configured to be in a forward-biasing state during a display phase of the pixel circuit for light-emitting and configured to be in a reverse-biasing state in a sensing phase of the pixel circuit to generate a sensing voltage; a driving transistor for driving the diode during the display phase; a readout transistor, with a gate receiving the sensing voltage during the sensing phase to serve as a source follower; first to seventh transistors, gate control signals applied to the gates of the first to seventh transistors respectively so that the pixel circuit switching between the display phase and the sensing phase; and a capacitor for storing a data voltage to be written to the diode in the display phase.

Abstract: Provided are an interaction method and apparatus in a live streaming room, a device, and a storage medium. The method comprises: in response to a trigger operation for a preset drawing entry on a live streaming room page, jumping to a graphic drawing page from the live streaming room page, a drawing trajectory set for a preset object being displayed on the graphical drawing page; when a drawing stroke on the graphic drawing page is received, matching the drawing stroke with the drawing trajectory; and if it is determined that the drawing stroke is successfully matched with the drawing trajectory, displaying prompt information about successful participation in a preset activity, the preset activity and the preset drawing entry having a correspondence.

Abstract: The disclosure describes methods of synthesis of pyridazinone compounds as thyroid hormone analogs and their prodrugs. Preferred methods according to the disclosure allow for large-scale preparation of pyridazinone compounds having high purity. In some embodiments, preferred methods according to the disclosure also allow for the preparation of pyridazinone compounds in better yield than previously used methods for preparing such compounds. Also disclosed are morphic forms of a pyridazinone compound. Further disclosed is a method for treating resistance to thyroid hormone in a subject having at least one TR? mutation.

Abstract: A device for treating a user's skin using plasma is provided. The device comprises a plasma generation assembly and a power supply. The plasma generation assembly comprises a discharge electrode including a first surface; a first dielectric material layer provided on the first surface of the discharge electrode and the first surface, a ground electrode surrounding the discharge electrode, and an insulation member spacing around the discharge electrode from the ground electrode. The power supply configured to apply power to the plasma generation assembly so that plasma is generated from the first surface of the discharge electrode to the ground electrode and between the first dielectric material layer and the user's skin.

Abstract: The present invention provides a smart wearable device, which is held on an upper body of a wearer by a plurality of contact pad sets, and has a connection unit, a first sensing module, a second sensing module, and an extension unit.

Abstract: Disclosed herein is a polyamide composition with improved hydrolytic resistance, which includes (a) 10 wt % to 40 wt % of polyamide 6, (b) more than 35 wt % to 50 wt % of poly-propylene, (c) 0.5 wt % to 10 wt % of a compatibilizer, and (d) 25 wt % to 50 wt % of reinforcing fillers, based on the total weight of the polyamide composition. The disclosed polyamide composition is suitable to prepare an article for cooling circuits in automobiles.

Abstract: The present disclosure provides a cabinet unit and a cabinet system. The cabinet unit includes a plurality of side walls consisting of a plurality of side wall units. A plurality of cabinet units are connected to one another to form the cabinet system.

Abstract: Methods, kits, and compositions are provided herein that can be used to treat ovarian cancer using an anti-CD47 antibody. The anti-CD47 antibody can be used alone or in combination with one or more additional agent such as chemotherapy.

Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: The disclosure relates to a quantum dot structure. The quantum dot structure includes a quantum dot and a cloud-like shell covering a portion of the quantum dot and having an irregular outer surface. The quantum dot includes: a core; a first shell discontinuously around a core surface of the core; and a second shell between the core and the first shell and encapsulating the core surface of the core, wherein the second shell has an irregular outer surface.

Abstract: An apparatus and a method for analyzing an electrical load include: receiving household electricity consumption data and household characteristic data of a user from a client device; selecting an electricity consumption analysis model according to household environment data of the user, and generating an electricity consumption tracking list according to a plurality of feature data of the household electricity consumption data and the household characteristic data via the electricity consumption analysis model; and transmitting the electricity consumption tracking list to the client device. An apparatus for modeling an electrical load includes: receiving a plurality of household electricity consumption data and of household characteristic data from client devices; and generating a plurality of electricity consumption analysis models according to the plurality of household electricity consumption data and the plurality of household characteristic data of the plurality of users.