Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

Abstract: A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an over-commit has occurred. In response to determining that the over-commit has occurred, the arbiter selects a broadcast command to be dropped based on a number of hops traversed through the data processing system by the broadcast command.

Abstract: A technique for operating a data processing system includes detecting that a processing unit within a first group of processing units in the data processing system has a hang condition. In response to detecting that the processing unit has a hang condition, a command issue rate for the first group of processing units is reduced. One or more other groups of processing units in the data processing system are notified that the first group of processing units has reduced the command issue rate for the first group of processing units. In response to the notifying, respective command issue rates of the other groups of processing units are reduced to reduce a number of commands received by the first group of processing units from the other groups of processing units.

Abstract: A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an over-commit has occurred. In response to determining that the over-commit has occurred, the arbiter selects a broadcast command to be dropped based on a number of hops traversed through the data processing system by the broadcast command.

Abstract: A technique for operating a data processing system includes detecting that a processing unit within a first group of processing units in the data processing system has a hang condition. In response to detecting that the processing unit has a hang condition, a command issue rate for the first group of processing units is reduced. One or more other groups of processing units in the data processing system are notified that the first group of processing units has reduced the command issue rate for the first group of processing units. In response to the notifying, respective command issue rates of the other groups of processing units are reduced to reduce a number of commands received by the first group of processing units from the other groups of processing units.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit is configured to be coupled to an interconnect of a multiprocessor system and is configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit is configured to be coupled to an interconnect of a multiprocessor system and is configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.

Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.