Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

Abstract: A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.

Abstract: A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. A first processing unit in the first processing node includes interconnect logic that processes a plurality of concurrently pending broadcast operations of differing broadcast scope. At least a first of the plurality of concurrently pending broadcast operations has a first scope limited to the first processing node, and at least a second of the plurality of concurrently pending broadcast operations has a second scope including the first processing node and the second processing node.

Abstract: A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The secondary interconnect trunk intersects the primary interconnect trunk at an intersection at which a bus control element is located. The bus control element includes a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk.

Abstract: A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

Abstract: A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.

Abstract: A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of the processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter.

Abstract: A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links.

Abstract: A data processing system includes an interconnect fabric, a protected resource having a plurality of banks each associated with a respective one of a plurality of address sets, a snooper that controls access to the resource, one or more masters that initiate requests, and interconnect logic coupled to the one or more masters and to the interconnect fabric. The interconnect logic regulates a rate of delivery to the snooper via the interconnect fabric of requests that target any one the plurality of banks of the protected resource.

Abstract: A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each of the plurality of first processing units is coupled to a respective one of the plurality of second processing units in the second processing node by a respective one of a plurality of point-to-point links.

Abstract: An integrated circuit (IC) processor chip apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter of that multiple processor chip.

Abstract: A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of the processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter.

Abstract: A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. A first processing unit in the first processing node includes interconnect logic that processes a plurality of concurrently pending broadcast operations of differing broadcast scope. At least a first of the plurality of concurrently pending broadcast operations has a first scope limited to the first processing node, and at least a second of the plurality of concurrently pending broadcast operations has a second scope including the first processing node and the second processing node.

Abstract: A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

Abstract: A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. The first processing units in the first processing node have a first mode in which the first processing units broadcast operations with a first scope limited to the first processing node and a second mode in which the first processing units of the first processing node broadcast operations with a second scope including the first processing node and the second processing node.

Abstract: A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

Abstract: A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. A first processing unit in the first processing node includes interconnect logic that processes a plurality of concurrently pending broadcast operations of differing broadcast scope. At least a first of the plurality of concurrently pending broadcast operations has a first scope limited to the first processing node, and at least a second of the plurality of concurrently pending broadcast operations has a second scope including the first processing node and the second processing node.

Abstract: A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.

Abstract: A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

Abstract: A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.