Abstract: Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

Abstract: Methods and systems for a multi-core processing system are described. In one embodiment, an apparatus comprises a first operating system (OS) core for managing kernel services. The first OS core includes a first physical memory, a first memory manager, and a first scheduler for scheduling a process to be executed, wherein the process is associated with a plurality of threads. At least two second OS cores comprise a second OS core and a third OS core. The apparatus includes a shared memory manager and a shared scheduler that are shared by the at least two second OS cores. The shared memory manager and the shared scheduler are configured to communicate with the first memory manager and the first scheduler, respectively, to initiate offloading of one or more of the threads from the first OS core to at least one of the at least two second OS cores for execution.

Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Abstract: The present disclosure describes techniques for switching tasks between heterogeneous cores. In some aspects it is determined that a task being executed by a first core of a processor can be executed by a second core of a processor, the second core having an instruction set that is different from that of the first core, and execution of the task is switched from the first core to the second core effective to decrease an amount of energy consumed by the processor.

Abstract: Systems, methods, and other embodiments associated with a processor configured with a zero power hibernation/sleep mode during which the processor consumes no power are described. According to one embodiment, a processor includes a power management logic. The power management logic is configured to receive a control signal requesting the processor to transition into a power saving mode that reduces power to the processor while retaining a current state of the processor. The power management logic is configured to store, in response to the control signal, a current state of components of the processor in a non-volatile memory. The power management logic is configured to adjust power to the processor to a zero power mode to place the processor into the power saving mode, wherein during the zero power mode the processor is receiving no power.

Abstract: The present disclosure describes techniques and apparatuses for switching between processor cache and random-access memory. In some aspects, the techniques and apparatuses are able to reduce die size of application-specific components by forgoing dedicated random-access memory (RAM). Instead of using dedicated RAM, a memory having a cache configuration is reconfigured to a RAM configuration during operations of the application-specific component and then, when the operations are complete, the memory is configured back to the cache configuration. Because many application-specific components already include memory having the cache configuration, reconfiguring this memory rather than including a dedicated RAM reduces die size for the application component.

Abstract: Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Abstract: An adaptive bus profiler is described. In embodiment(s), data traffic that is communicated on an adaptive bus can be monitored, and projected data traffic that is scheduled for communication via the adaptive bus can be determined. An adaptive bus profile can be determined based on the data traffic and the projected data traffic. A reconfiguration of a bus width of the adaptive bus can be initiated based on the adaptive bus profile.

Abstract: Methods and systems for a multi-core operating system are provided. A first operating system (OS) core can manage kernel services. The first OS core may include a first memory manager and a first scheduler for scheduling a process to be executed. The process can be associated with a plurality of threads. One or more second operating system (OS) cores can share a shared memory manager and a shared scheduler, and the shared memory manager and the shared scheduler can communicate with the first memory manager and the first scheduler to facilitate offloading of one or more of a plurality of threads from the first OS core to at least one of the one or more second OS cores for execution. The first OS core can be asymmetric with respect to the one or more second operating system cores, and the one or more second operating system cores may be asymmetric with respect to each other.

Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Abstract: An adaptive bus profiler is described. In embodiment(s), data traffic that is communicated on an adaptive bus can be monitored, and projected data traffic that is scheduled for communication via the adaptive bus can be determined. An adaptive bus profile can be determined based on the data traffic and the projected data traffic. The data traffic that is communicated on the adaptive bus can be suspended to reconfigure a bus width of the adaptive bus based on the adaptive bus profile.

Abstract: A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.

Abstract: Embodiments of a method and system for heterogeneous memory control are disclosed. The embodiments include components of a Memory Manager that receive usage information of a memory subsystem of a host system, the memory subsystem including internal memory and external memory. The Memory Manager also receives client information of one or more clients that are coupled to and/or integrated with the host system. A request or call for internal memory is also received at the Memory Manager from the clients. The Memory manager automatically controls the memory in accordance with one or more of the request, the usage information and the client information. The control includes allocating a portion of the internal memory to the client, remapping one or more areas of internal memory from a first client to a second client, and/or reorganizing the memory by remapping external memory to internal memory. Other embodiments are described and claimed.

Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Abstract: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Abstract: A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.

Abstract: A disclosed method involves initializing a performance profiler of a processing system. The performance profiler may include performance profile parameters for a power management policy for the processing system. The method also involves retrieving performance metrics for the processing system from a performance monitoring unit (PMU) of the processing system, in response to a determination that performance details should be collected. A current performance state of the processing system may be determined, based at least in part on the performance profile parameters and the performance metrics from the PMU. The current performance state may then be communicated to a policy manager of the processing system. Other embodiments are disclosed and claimed.

Abstract: Embodiments of a method and system for heterogeneous memory control are disclosed. The embodiments include components of a Memory Manager that receive usage information of a memory subsystem of a host system, the memory subsystem including internal memory and external memory. The Memory Manager also receives client information of one or more clients that are coupled to and/or integrated with the host system. A request or call for internal memory is also received at the Memory Manager from the clients. The Memory manager automatically controls the memory in accordance with one or more of the request, the usage information and the client information. The control includes allocating a portion of the internal memory to the client, remapping one or more areas of internal memory from a first client to a second client, and/or reorganizing the memory by remapping external memory to internal memory. Other embodiments are described and claimed.

Abstract: A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.