Patents by Inventor Qadeer A. Qureshi
Qadeer A. Qureshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220277800Abstract: A memory system includes a memory that provides digital data and a built-in self-test (BIST) circuit for testing the memory for determining defective storage units of the memory. The memory system has a data output for providing data from the memory to an external system. The data output of the memory system has a first bit width. The memory has a data output that has a second bit width that is greater than the first bit width. The BIST circuit has a data input that is of the second bit width.Type: ApplicationFiled: March 1, 2021Publication date: September 1, 2022Inventors: Rodrigo Pascoal Zeli, Qadeer Qureshi, Henning Fritz Spruth, Reinaldo Silveira
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Patent number: 9595350Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.Type: GrantFiled: November 5, 2012Date of Patent: March 14, 2017Assignee: NXP USA, INC.Inventors: Henning F. Spruth, Qadeer A. Qureshi, Reinaldo Silveira
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Patent number: 9418741Abstract: A content addressable memory (CAM) and methods of operating a CAM are provided. The method for operating a CAM includes: during a first mode, performing a search function in a CAM bit array, the search result output at a match port of the CAM bit array; and during a second mode, columnwise reading data in the CAM bit array, the read column data output at the match data port of the CAM bit array. The method may include writing the CAM bit array with a predetermined data pattern. The method may further include providing an indication of pass/fail based upon comparing the read column data with expected data.Type: GrantFiled: August 25, 2015Date of Patent: August 16, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, Qadeer A. Qureshi, Henning F. Spruth, Reinaldo Silveira
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Patent number: 9384856Abstract: A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.Type: GrantFiled: December 11, 2013Date of Patent: July 5, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Henning F. Spruth, Qadeer A. Qureshi, Reinaldo Silveira
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Publication number: 20150162098Abstract: A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Inventors: HENNING F. SPRUTH, Qadeer A. Qureshi, Reinaldo Silveira
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Publication number: 20140129883Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Henning F. Spruth, Qadeer A. Qureshi, Reinaldo Silveira
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Patent number: 7616509Abstract: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.Type: GrantFiled: July 13, 2007Date of Patent: November 10, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, Sushama Davar, Thomas Jew
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Patent number: 7483327Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.Type: GrantFiled: March 2, 2006Date of Patent: January 27, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, James D. Burnett, Jack M. Higman, Thomas Jew
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Publication number: 20090016140Abstract: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Inventors: Qadeer A. Qureshi, Sushama Davar, Thomas Jew
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Patent number: 7444557Abstract: A memory not only uses redundant cells but also redundant references to reduce the likelihood of a failure. In one approach a failure in a reference can cause both the primary cell as well as the redundant cell to be ineffective. To overcome this potential problem two references for each bit are employed. In one form, the primary cell of a first bit is compared to one reference and the redundant cell of the first bit is compared to another reference. The primary and redundant cell of a second bit can use these two references as well. In another aspect, two references are placed in parallel for both the primary and redundant cell of the bit.Type: GrantFiled: July 15, 2004Date of Patent: October 28, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Alexander B. Hoefler, Qadeer A. Qureshi
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Patent number: 7362645Abstract: Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).Type: GrantFiled: September 30, 2004Date of Patent: April 22, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, John J. Vaglica, William C. Moyer, Ryan D. Bedwell
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Patent number: 7295484Abstract: A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.Type: GrantFiled: March 13, 2007Date of Patent: November 13, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Arnaldo R. Cruz, Qadeer A. Qureshi
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Patent number: 7245527Abstract: A non-volatile memory system (230) includes a magnetoresistive random access memory (MRAM) (232) including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory (234) including a plurality of floating-gate memory cells, and a controller (236) coupled to the MRAM (232) and to the floating-gate nonvolatile memory (234). The controller (236) is adapted to be coupled to a system bus (220) and controls a selected one of the MRAM (232) and the floating-gate nonvolatile memory (234) in response to an access initiated from the system bus (220).Type: GrantFiled: May 16, 2005Date of Patent: July 17, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, Thomas Jew, Curtis F. Wyman
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Publication number: 20070153606Abstract: A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.Type: ApplicationFiled: March 13, 2007Publication date: July 5, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Arnaldo Cruz, Qadeer Qureshi
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Patent number: 7206244Abstract: A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.Type: GrantFiled: December 1, 2004Date of Patent: April 17, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Arnaldo R. Cruz, Qadeer A. Qureshi
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Publication number: 20060256610Abstract: A non-volatile memory system (230) includes a magnetoresistive random access memory (MRAM) (232) including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory (234) including a plurality of floating-gate memory cells, and a controller (236) coupled to the MRAM (232) and to the floating-gate nonvolatile memory (234). The controller (236) is adapted to be coupled to a system bus (220) and controls a selected one of the MRAM (232) and the floating-gate nonvolatile memory (234) in response to an access initiated from the system bus (220).Type: ApplicationFiled: May 16, 2005Publication date: November 16, 2006Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Qadeer Qureshi, Thomas Jew, Curtis Wyman
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Publication number: 20060114734Abstract: A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.Type: ApplicationFiled: December 1, 2004Publication date: June 1, 2006Inventors: Arnaldo Cruz, Qadeer Qureshi
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Publication number: 20060085702Abstract: Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).Type: ApplicationFiled: September 30, 2004Publication date: April 20, 2006Inventors: Qadeer Qureshi, John Vaglica, William Moyer, Ryan Bedwell
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Publication number: 20060039215Abstract: A memory not only uses redundant cells but also redundant references to reduce the likelihood of a failure. In one approach a failure in a reference can cause both the primary cell as well as the redundant cell to be ineffective. To overcome this potential problem two references for each bit are employed. In one form, the primary cell of a first bit is compared to one reference and the redundant cell of the first bit is compared to another reference. The primary and redundant cell of a second bit can use these two references as well. In another aspect, two references are placed in parallel for both the primary and redundant cell of the bit.Type: ApplicationFiled: July 15, 2004Publication date: February 23, 2006Inventors: Alexander Hoefler, Qadeer Qureshi
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Patent number: 6917555Abstract: Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.Type: GrantFiled: September 30, 2003Date of Patent: July 12, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Ryan D. Bedwell, Christopher K. Y. Chun, Qadeer A. Qureshi, John J. Vaglica