Abstract: A method and apparatus for reading a timer with an asynchronous circuit. A computer system is provided having a system clock and an asynchronous timer clock. The computer system includes a counter clocking from the timer clock and a latch coupled to output of the counter. First logic, synchronized to the timer clock, is coupled to control the latch responsive to a control signal from the computer system. Second logic synchronized to the system clock and coupled to the first logic is configured to provide an indication to the computer system of when the system can read the latched data and be assured of its validity. The computer system will thereby be prevented from reading the timer before it has stabilized.

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: A bus interface timing unit responsive to a system clock signal having a frequency that is selectable among a plurality of frequencies. The bus interface timing unit provides timing signals to a bus interface unit that performs functions involving control signals having predetermined timing requirements, such timing requirements being substantially independent of the frequency of the system clock signal. The bus interface timing unit includes a signal generator (20) which is responsive to the system clock signal, and which generates the control signals. These control signals include at least one event signal controlling a time duration in which a predetermined event occurs. Also included is a control unit (10), responsive to a signal representative of the selected frequency of the system clock signal, that controls the signal generator such that the event signal timing is generated in accordance with the predetermined requirements the selected frequencies.