Abstract: A field emission cathode structure includes a dielectric layer, a field emission unit, a grid electrode, and a conductive layer. The dielectric layer is positioned on the insulating substrate and defines a cavity. A field emission unit is attached on the cathode electrode and received in the cavity of the dielectric layer. The field emission unit is electrically attached to the cathode electrode. The grid electrode is located on the dielectric layer, and electrons emitted from the field emission unit emit through the grid electrode. The conductive layer is electrically attached to the grid electrode and insulated from the field emission unit. A field emission display device using the above-mentioned field emission cathode structure is also provided.

Abstract: A method for surface treating a cold cathode includes the following steps. A cold cathode is provided and the cold cathode includes a plurality of field emitters. A liquid glue is placed on a surface of the cold cathode. The liquid glue is cured to form solid glue on the surface of the cold cathode. The solid glue is removed to allow the plurality of field emitters to stand upright.

Abstract: The field emission cathode device includes an insulating substrate with a number of cathodes mounted thereon. A number of field emission units are mounted on the cathodes. A dielectric layer is disposed on the insulating substrate and defines a number of voids corresponding to the field emission units. The dielectric layer has an upper and lower section and disposed on the insulating substrate. The dielectric layer defining a plurality of voids corresponding to the field emission units. A number of grids disposed between the upper and lower sections, and wherein each grid are secured by the upper and lower sections of the dielectric layer.

Abstract: Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages using thermometer coding. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs, wherein the capacitors are switched according to a thermometer code to reduce differential converter non-linearity.

Abstract: The present invention relates to a device for preparing assay samples using a number of microscope slides. Each slide has a number of assay reaction surface locations spaced on the planar surface of the slide. In preferred embodiments, the device comprises, in part, a microscope slide holder that has the exterior dimensions of a SBS standard microplate, such as a 96 well plate. The device accepts conventional microscope slides equipped with sixteen microarray surfaces spaced nine millimeters apart on center, or four for a 96 well plate. Individual chamber plates are placed on top of the slides, creating an individual well above each assay reaction surface location. In preferred embodiments, each assay reaction surface location can comprise a microarray of multiple reactive sites. Thus, parallel processing can be done of samples for genomic or proteomic profiling.

Abstract: Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs. In one implementation, the capacitors are switched according to a thermometer code to reduce differential converter non-linearity, and the first subconverter stage gain is reduced to improve the conversion system bandwidth.

Abstract: Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages using thermometer coding. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs, wherein the capacitors are switched according to a thermometer code to reduce differential converter non-linearity.

Abstract: Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs. In one implementation, the capacitors are switched according to a thermometer code to reduce differential converter non-linearity, and the first subconverter stage gain is reduced to improve the conversion system bandwidth.