Abstract: Methods, systems, and devices for transferring memory system data to a host system are described. A system may be configured for transferring information between a memory system and a host system in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transmit the identified information to the host system. Such information transmitted to the host system may be returned to the memory system to support memory system operation after exiting the reduced power mode. In some examples, such information exchanged between the memory system and the host system may be associated with a processing capability of the memory system, and the described operations may be referred to as suspending memory system processing information to a host system.

Abstract: Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.

Abstract: Disclosed in some examples are memory devices which increase a parallelism of host operations of a memory device. While a first block of data from a first stripe in a first memory die is being read, blocks of data belonging to a second stripe stored in memory dies other than the first memory die are concurrently read. This includes reading the parity value of the second stripe. The parity data, along with the blocks of data from the second stripe from dies other than the first die are then used to determine the block of data of the second stripe stored in the first memory die without actually reading the value from the block in the first memory die. This reconstruction may be done in parallel with additional read operations for other data performed on the first die.

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

Abstract: A memory device includes a hardware suspend mechanism configured to place a component of a memory controller into a lower power mode while a memory operation is being completed. A timer is provided to wakeup the CPU out of the lower power mode; and hardware interrupts can be used in determining to either enter or wake from the lower power mode. Memory monitoring circuitry is provided to estimate the duration of memory operations; and timers are provided to wake the component in the absence of hardware interrupts or additional commands.

Abstract: A feature can be defined to allow data attributes to be dynamically assigned to data in a storage device. For example, a feature referred to as a “datagroup” is introduced. A datagroup is defined as a grouping of a range of local block addresses. A storage device can be divided into a number of datagroups. Each datagroup can have its own data attributes configuration, which can have a specified number of bits. A new command is defined to allow a host to dynamically assign attributes of datagroups of a storage device. For example, the command can provide for dynamically assigning datagroup attributes by sending a byte-mapping table in the command from the host to the storage device.

Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

Abstract: Disclosed in some examples are memory devices which increase a parallelism of host operations of a memory device. While a first block of data from a first stripe in a first memory die is being read, blocks of data belonging to a second stripe stored in memory dies other than the first memory die are concurrently read. This includes reading the parity value of the second stripe. The parity data, along with the blocks of data from the second stripe from dies other than the first die are then used to determine the block of data of the second stripe stored in the first memory die without actually reading the value from the block in the first memory die. This reconstruction may be done in parallel with additional read operations for other data performed on the first die.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a pattern of host accessing the device are discussed. The host access pattern can be represented by how frequent the device is in idle states free of active host access. An exemplary memory device includes a memory controller to track a count of idle periods during a specified time window, and to adjust an amount of memory space to be freed by a GC operation in accordance with the count of idle periods. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the count of idle periods during the specified time window.

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

Abstract: A method and systems for controlling and directing a means of transportation to autonomously navigate to a target location are provided. The method includes receiving measurements from one or more sensors of the means of transportation; building a route based on the measurement received for the means of transportation to navigate to a target location; generating localization estimation associated with the route built; generating a global path based on the route and the localization estimation; and performing local planning for directing the means of transportation to the target location while avoiding surrounding static or dynamic obstacles. The one or more sensors include a LiDAR sensor and an odometry sensor.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.

Abstract: Methods, systems, and devices related to host identification for a memory system are described. A memory system may receive an index value from a host system that is associated with an identification of the host system. The memory system may identify one or more operating parameter associated with the index value based on receiving the index value. The memory system controller may configure the memory system to utilize one or more operating parameters associated with the index value based on identifying the operating parameters. The memory system may output an indication to the host system that the operating parameters associated with the index value are configured to be utilized by the memory system.

Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

Abstract: Methods, systems, and devices for memory systems having a selectively interfaceable memory subsystem are described. A memory system may include the memory subsystem that may be configurable to provide volatile storage, nonvolatile storage, or both to a host system. The memory subsystem may include a plurality of ports each capable of communicating with the host system using different interfaces. The memory subsystem may be dynamically configurable to perform different functions based on the demands of the host system. In some examples, memory systems described herein may include a first memory subsystem to provide nonvolatile storage to the host system, a second memory subsystem to provide volatile storage to the host system, and a third memory subsystem configurable to provide volatile storage or nonvolatile storage or both to the host system.

Abstract: Methods, systems, and devices for memory data correction using multiple error control operations are described. A single command may be received to correct an error detected in data stored by a memory array. A first error control operation and a second error control operation may be implemented based on the single command. The first error control operation may be performed on the data stored by the memory array using one or more different reference voltages to read the data. The error may be determined to remain in the data after performing the first error control operation. The second error control operation may then be performed on the data stored by the memory array. The second error control operation may use one or more voltage distributions associated with the memory cells of the memory array.

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.