Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to co-integration of self-aligned and non-self aligned heterojunction bipolar transistors and methods of manufacture. The structure includes at least two heterojunction bipolar transistor (HBT) devices integrated onto a same wafer with different epitaxial base profiles. An intrinsic base epitaxy for a second device of the at least two HBT devices acts as an extrinsic base for a first device of the at least two HBT devices.