Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A multi-layer semiconductor device (or structure) includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces. Additionally, each of the at least two semiconductor structures includes a first section having first and second opposing surfaces and a plurality of electrical connections extending between select portions of the first and second surfaces. Each of the at least two semiconductor structures also includes a second section having first and second opposing surfaces, with the first surface of the second section disposed over and coupled to the second surface of the first section. Methods for fabricating a multi-layer semiconductor structure from a plurality of semiconductor structures are also provided.

Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corres ponding method for fabricating a semiconductor structure is also provided.

Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.

Abstract: A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.

Abstract: A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.

Abstract: A circuitized substrate which utilizes at least one internal (embedded) resistor as part thereof, the resistor comprised of a material including resin and a quantity of powders of nano-particle and/or micro-particle sizes. The resistor serves to decrease the capacitance in the formed circuit while only slightly increasing the high frequency resistance, thereby improving circuit performance through the substantial elimination of some discontinuities known to exist in structures like these. An electrical assembly (substrate and at least one electrical component) is also provided.

Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

Abstract: A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.

Abstract: A structure for minimizing resistance between a semi-insulating x-ray detector crystal and an electrically conducting substrate. Electrical contact pads are disposed on the detector crystal and on the substrate with an electrical interconnect between the contact pads formed from a conductive adhesive and washed solder in electrical and mechanical communication with the pads.

Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.

Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.

Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.