Patents by Inventor Radha Sundararajan

Radha Sundararajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8486798
    Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.
    Type: Grant
    Filed: February 5, 2012
    Date of Patent: July 16, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Zhiying Chen, Jianping Zhao, Lee Chen, Merritt Funk, Radha Sundararajan
  • Patent number: 8343371
    Abstract: The invention can provide apparatus and methods of processing a substrate in real-time using a Quasi-Neutral Beam (Q-NB) curing system to improve the etch resistance of photoresist layer. In addition, the improved photoresist layer can be used to more accurately control gate and/or spacer critical dimensions (CDs), to control gate and/or spacer CD uniformity, and to eliminate line edge roughness (LER) and line width roughness (LWR).
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: January 1, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Lee Chen, Radha Sundararajan
  • Publication number: 20120248310
    Abstract: An ion energy analyzer for determining an ion energy distribution of a plasma and comprising an entrance grid, a selection grid, and an ion collector. The entrance grid includes a first plurality of openings dimensioned to be less than a Debye length for the plasma. The ion collector is coupled to the entrance grid via a first voltage source. The selection grid is positioned between the entrance grid and the ion collector and is coupled to the entrance grid via a second voltage source. An ion current meter is coupled to the ion collector to measure an ion flux onto the ion collector and transmit a signal related thereto.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 4, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Lee Chen, Barton Lane, Merritt Funk, Jianping Zhao, Radha Sundararajan
  • Publication number: 20120248322
    Abstract: A method of generating a signal representing with an ion energy analyzer for use in determining an ion energy distribution of a plasma. The ion energy analyzer, used for determining an ion energy distribution of a plasma, includes a first grid and a second grid that is spaced away from and electrically isolated from the first grid. The first grid forms a first surface of the ion energy analyzer and is positioned to be exposed to the plasma. The first grid includes a first plurality of openings, which are dimensioned to be less than a Debye length for the plasma. A voltage source and an ion current meter are operably coupled to the second grid, the latter of which is configured to measure an ion flux onto the ion collector and to transmit a signal that represents the measured ion flux. The method includes selectively and variably biasing the second grid relative to the first grid.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 4, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Lee Chen, Barton Lane, Jianping Zhao, Radha Sundararajan
  • Publication number: 20120252141
    Abstract: The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Radha Sundararajan, Merritt Funk, Lee Chen, Barton Lane
  • Publication number: 20120248311
    Abstract: A process by which an ion energy analyzer is manufactured includes processing a first substrate to form an entrance grid having a first channel and a first plurality of openings extending therethrough. A second substrate is processed to form a selection grid having a second channel therein and a second plurality of openings extending therethrough. A third substrate is processed to form an ion collector having a third channel therein. The entrance grid is operably coupled to, and electrically isolated from, the selection grid, which is, in turn, operably coupled to, and electrically isolated from, the ion collector.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 4, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Lee Chen, Barton Lane, Jianping Zhao, Radha Sundararajan
  • Patent number: 8183062
    Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: May 22, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager
  • Patent number: 8019458
    Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: September 13, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
  • Patent number: 7988813
    Abstract: A method and system for dynamically controlling a process chemistry above a substrate is described. The system for adjusting the process chemistry comprises a ring configured to surround a peripheral edge of a substrate in a vacuum processing system. The ring comprises one or more gas distribution passages formed within the ring and configured to supply an additive process gas through an upper surface of the ring to the peripheral region of the substrate, wherein the one or more gas distribution passages are configured to be coupled to one or more corresponding gas supply passages formed within the substrate holder upon which the ring rests.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: August 2, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Lee Chen, Radha Sundararajan, Merritt Funk
  • Publication number: 20110174606
    Abstract: The invention can provide apparatus and methods of processing a substrate in real-time using a Quasi-Neutral Beam (Q-NB) curing system to improve the etch resistance of photoresist layer. In addition, the improved photoresist layer can be used to more accurately control gate and/or spacer critical dimensions (CDs), to control gate and/or spacer CD uniformity, and to eliminate line edge roughness (LER) and line width roughness (LWR).
    Type: Application
    Filed: January 15, 2010
    Publication date: July 21, 2011
    Applicant: Tokyo Electron Limited
    Inventors: Merritt Funk, Lee Chen, Radha Sundararajan
  • Patent number: 7967995
    Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 28, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Daniel Prager, Asao Yamashita
  • Patent number: 7939450
    Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: May 10, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Asao Yamashita, Merritt Funk, Daniel J. Prager, Lee Chen, Radha Sundararajan
  • Patent number: 7899637
    Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 1, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
  • Patent number: 7894927
    Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: February 22, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
  • Publication number: 20100214545
    Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 26, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Merritt Funk, Daniel J. Prager, Asao Yamashita, Radha Sundararajan
  • Patent number: 7713758
    Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: May 11, 2010
    Assignee: Tokyo Electon Limited
    Inventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
  • Publication number: 20100081285
    Abstract: The invention can provide apparatus and methods of processing a substrate in real-time using subsystems and processing sequences created to improve the etch resistance of photoresist materials. In addition, the improved photoresist layer can be used to more accurately control gate and/or spacer critical dimensions (CDs), to control gate and/or spacer CD uniformity, and to eliminate line edge roughness (LER) and line width roughness (LWR).
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Lee Chen, Merritt Funk, Radha Sundararajan
  • Patent number: 7674636
    Abstract: A method and apparatus are provided to control the radial or non-radial temperature distribution across a substrate during processing to compensate for non-uniform effects, including radial and angular non-uniformities arising from system variations, or process variations, or both. The temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck to vary heat conduction across the wafer. Backside gas flow, of helium, for example, is dynamically varied across the chuck to control the uniformity of processing of the wafer. Ports in the support are grouped, and gas to or from the groups is separately controlled by different valves responsive to a controller that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: March 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Radha Sundararajan, Lee Chen, Merritt Funk
  • Publication number: 20100036514
    Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 11, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
  • Publication number: 20100036518
    Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 11, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee