Patents by Inventor Radha Sundararajan
Radha Sundararajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7623978Abstract: A method of assessing damage of a dual damascene structure includes obtaining a wafer after the wafer has been processed using a dual damascene process. A first damage-assessment procedure is performed on the wafer using an optical metrology process to gather damage-assessment data for a first set of measurements sites on the wafer. For each measurement site in the first set of measurement sites, the optical metrology process determines an amount of damage of a damaged area of a periodic grating in the measurement site. The damage-assessment data includes the amount of damage determined by the optical metrology process. A first damage-assessment map is created for the dual damascene process. The first damage-assessment includes the damage-assessment data and the locations of the first set of measurement sites on the wafer. One or more values in the damage-assessment map are compared to damage-assessment limits established for the dual damascene process to identify the wafer as a damaged or undamaged wafer.Type: GrantFiled: March 30, 2006Date of Patent: November 24, 2009Assignee: Tokyo Electron LimitedInventors: Kevin Lally, Merritt Funk, Radha Sundararajan
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Patent number: 7619731Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology includes directing an incident beam on the damaged structure. A diffracted beam is received from the damaged structure. The received diffracted beam is processed to determine a profile of an undamaged portion of the damaged structure and to measure an amount of dielectric damage of the damaged structure.Type: GrantFiled: March 30, 2006Date of Patent: November 17, 2009Assignee: Tokyo Electron LimitedInventors: Kevin Lally, Merritt Funk, Radha Sundararajan
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Publication number: 20090242513Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Daniel Prager, Asao Yamashita
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Patent number: 7576851Abstract: A method of creating a library for measuring a plurality of damaged structures formed on a semiconductor wafer using optical metrology includes directing an incident beam on a first damaged structure. The first damaged structure was formed by modifying at least one process parameter in a dual damascene procedure. A diffracted beam is received from the first damaged structure. A measured diffraction signal is obtained based on the received diffracted beam. A first simulated diffraction signal is calculated. The first simulated diffraction signal corresponds to a hypothetical profile of the first damaged structure. The hypothetical profile includes an undamaged dielectric portion and a damaged dielectric portion. The measured diffraction signal is compared to the first simulated diffraction signal.Type: GrantFiled: March 30, 2006Date of Patent: August 18, 2009Assignee: Tokyo Electron LimitedInventors: Kevin Lally, Merritt Funk, Radha Sundararajan
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Patent number: 7567700Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: GrantFiled: March 28, 2006Date of Patent: July 28, 2009Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: Merritt Funk, Radha Sundararajan, Daniel Joseph Prager, Wesley Natzle
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Publication number: 20090082983Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel J. Prager, Lee Chen, Radha Sundararajan
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Publication number: 20090081815Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel J. Prager, Lee Chen, Radha Sundararajan
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Patent number: 7502709Abstract: A method of monitoring a dual damascene procedure that includes calculating a pre-processing confidence map for a damascene process, the pre-processing confidence map including confidence data for a first set of dies on the wafer. An expanded pre-processing measurement recipe is established for the damascene process when one or more values in the pre-processing confidence map are not within confidence limits established for the damascene process. A reduced pre-processing measurement recipe for the first damascene process is established when one or more values in the pre-processing confidence map are within confidence limits established for the damascene process.Type: GrantFiled: March 28, 2006Date of Patent: March 10, 2009Assignees: Tokyo Electron, Ltd., International Business Machines CorporationInventors: Merritt Funk, Radha Sundararajan, Daniel Joseph Prager, Wesley Natzle
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Patent number: 7477960Abstract: A method for implementing FDC in an APC system including receiving an FDC model from memory; providing the FDC model to a process model calculation engine; computing a vector of predicted dependent process parameters using the process model calculation engine; receiving a process recipe comprising a set of recipe parameters, providing the process recipe to a process module; executing the process recipe to produce a vector of measured dependent process parameters; calculating a difference between the vector of predicted dependent process parameters and the vector of measured dependent process parameters; comparing the difference to a threshold value; and declaring a fault condition when the difference is greater than the threshold value.Type: GrantFiled: February 16, 2005Date of Patent: January 13, 2009Assignee: Tokyo Electron LimitedInventors: James E. Willis, Merritt Funk, Kevin Lally, Kevin Pinto, Masayuki Tomoyasu, Raymond Peterson, Radha Sundararajan
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Publication number: 20080311688Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Radha Sundararajan, Lee Chen
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Publication number: 20080311687Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
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Publication number: 20080223873Abstract: A method and system for dynamically controlling a process chemistry above a substrate is described. The system for adjusting the process chemistry comprises a ring configured to surround a peripheral edge of a substrate in a vacuum processing system. The ring comprises one or more gas distribution passages formed within the ring and configured to supply an additive process gas through an upper surface of the ring to the peripheral region of the substrate, wherein the one or more gas distribution passages are configured to be coupled to one or more corresponding gas supply passages formed within the substrate holder upon which the ring rests.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Applicant: Tokyo Electron LimitedInventors: Lee Chen, Radha Sundararajan, Merritt Funk
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Publication number: 20080227227Abstract: A method and apparatus are provided to control the radial or non-radial temperature distribution across a substrate during processing to compensate for non-uniform effects, including radial and angular non-uniformities arising from system variations, or process variations, or both. The temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck to vary heat conduction across the wafer. Backside gas flow, of helium, for example, is dynamically varied across the chuck to control the uniformity of processing of the wafer. Ports in the support are grouped, and gas to or from the groups is separately controlled by different valves responsive to a controller that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Radha Sundararajan, Lee Chen, Merritt Funk
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Publication number: 20080137078Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.Type: ApplicationFiled: January 28, 2008Publication date: June 12, 2008Applicant: Tokyo Electron LimitedInventors: Kevin LALLY, Merritt FUNK, Radha SUNDARARAJAN
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Patent number: 7324193Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.Type: GrantFiled: March 30, 2006Date of Patent: January 29, 2008Assignee: Tokyo Electron LimitedInventors: Kevin Lally, Merritt Funk, Radha Sundararajan
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Publication number: 20070238201Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC layer data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070237383Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070229807Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.Type: ApplicationFiled: March 30, 2006Publication date: October 4, 2007Applicant: Tokyo Electron, Ltd.Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
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Publication number: 20070231930Abstract: A method of monitoring a dual damascene procedure that includes calculating a pre-processing confidence map for a damascene process, the pre-processing confidence map including confidence data for a first set of dies on the wafer. An expanded pre-processing measurement recipe is established for the damascene process when one or more values in the pre-processing confidence map are not within confidence limits established for the damascene process. A reduced pre-processing measurement recipe for the first damascene process is established when one or more values in the pre-processing confidence map are within confidence limits established for the damascene process.Type: ApplicationFiled: March 28, 2006Publication date: October 4, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070232045Abstract: A method of assessing damage of a dual damascene structure includes obtaining a wafer after the wafer has been processed using a dual damascene process. A first damage-assessment procedure is performed on the wafer using an optical metrology process to gather damage-assessment data for a first set of measurements sites on the wafer. For each measurement site in the first set of measurement sites, the optical metrology process determines an amount of damage of a damaged area of a periodic grating in the measurement site. The damage-assessment data includes the amount of damage determined by the optical metrology process. A first damage-assessment map is created for the dual damascene process. The first damage-assessment includes the damage-assessment data and the locations of the first set of measurement sites on the wafer. One or more values in the damage-assessment map are compared to damage-assessment limits established for the dual damascene process to identify the wafer as a damaged or undamaged wafer.Type: ApplicationFiled: March 30, 2006Publication date: October 4, 2007Applicant: Tokyo Electron, Ltd.Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan