Patents by Inventor Rajan Goyal

Rajan Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method to provide non-coherent access to a coherent memory system
    Patent number: 9569366
    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: February 14, 2017
    Assignee: Cavium, Inc.
    Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari
  • Generating a non-deterministic finite automata (NFA) graph for regular expression patterns with advanced features
    Patent number: 9563399
    Abstract: In an embodiment, a method of compiling a pattern into a non-deterministic finite automata (NFA) graph includes examining the pattern for a plurality of elements and a plurality of node types. Each node type can correspond with an element. Each element of the pattern can be matched at least zero times. The method further includes generating a plurality of nodes of the NFA graph. Each of the plurality of nodes can be configured to match for one of the plurality of elements. The node can indicate the next node address in the NFA graph, a count value, and/or node type corresponding to the element. The node can also indicate the element representing a character, character class or string. The character can also be a value or a letter.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: February 7, 2017
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • METHOD AND APPARATUS FOR VIRTUALIZATION
    Publication number: 20170024159
    Abstract: A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.
    Type: Application
    Filed: June 24, 2016
    Publication date: January 26, 2017
    Inventors: Muhammad Raghib Hussain, Rajan Goyal, Richard Kessler
  • Multi-rule approach to encoding a group of rules
    Patent number: 9544402
    Abstract: A multi-rule approach for encoding rules grouped in a rule chunk is provided. The approach includes a multi-rule with a multi-rule header representing headers of the rules and, in some cases, dimensional data representing dimensional data of the rules. The approach further includes disabling dimension matching of always matching dimensions, responding to an always match rule with a match response without matching, interleaving minimum/maximum values in a range field, interleaving value/mask values in a mask field, and for a given rule of rule chunk, encoding a priority field at the end of dimension data stored for the rule in the multi-rule. Advantageously, this approach provides efficient storage of rules and enables the efficient comparison of rules to keys.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 10, 2017
    Assignee: CAVIUM, INC.
    Inventors: Frank Worrell, Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Phased bucket pre-fetch in a network processor
    Patent number: 9531723
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. Based on a prefetch status, a selection of the subset of rules are retrieved for rule matching. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: December 27, 2016
    Assignee: Cavium, Inc.
    Inventors: Gregg A. Bouchard, Rajan Goyal
  • Multi-host processing
    Patent number: 9531647
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from multiple hosts, manages traffic among the hosts, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 27, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Troy S. Dahlmann, Jeffrey Richard Hardesty, Karen A. Szypulski
  • Method and apparatus for managing processing thread migration between clusters within a processor
    Patent number: 9531690
    Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: December 27, 2016
    Assignee: Cavium, Inc.
    Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Satyanarayana Lakshmipathi Billa
  • Method and apparatus for assigning resources used to manage transport operations between clusters within a processor
    Patent number: 9525630
    Abstract: A method, and corresponding apparatus, of assigning processing resources used to manage transport operations between a first memory cluster and one or more other memory clusters, include receiving information indicative of allocation of a subset of processing resources in each of the one or more other memory clusters to the first memory cluster, storing, in the first memory cluster, the information indicative of resources allocated to the first memory cluster, and facilitating management of transport operations between the first memory cluster and the one or more other memory clusters based at least in part on the information indicative of resources allocated to the first memory cluster.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: December 20, 2016
    Assignee: Cavium, Inc.
    Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn
  • Anchored patterns
    Patent number: 9514246
    Abstract: A method and apparatus relate to recognizing anchored patterns from an input stream. Patterns from a plurality of given patterns are marked as anchored patterns. An anchored state tree for the anchored patterns of the plurality of given patterns is built, including nodes representing a state of the anchored state tree. For each node of the anchored state tree, a failure value equivalent to a node representing a state in an unanchored state tree representing unanchored patterns of the plurality of given patterns is determined.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: December 6, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • System and method to traverse a non-deterministic finite automata (NFA) graph generated for regular expression patterns with advanced features
    Patent number: 9507563
    Abstract: In one embodiment, a method of walking a non-deterministic finite automata (NFA) graph representing a pattern includes extracting a node type and an element from a node of the NFA graph. The method further includes matching a segment of a payload for the element by matching the payload for the element at least zero times, the number of times based on the node type.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: November 29, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Lookup front end packet output processor
    Patent number: 9497117
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: November 15, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski
  • Traversal with arc configuration information
    Patent number: 9495479
    Abstract: An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc may also include a nodal bit map including structural information of a node to which the valid arc points to. A walker process may utilize the nodal bit map to determine if a memory access is necessary. The nodal bit map reduces the number of external memory access and therefore reduces system run time.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 15, 2016
    Assignee: Cavium, Inc.
    Inventor: Rajan Goyal
  • Processing of finite automata based on a node cache
    Patent number: 9438561
    Abstract: Nodes of a per-pattern NFA may be stored amongst one or more of a plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels. At least one processor may be configured to cache one or more nodes of the per-pattern NFA in the node cache based on a cache miss of a given node of the one or more nodes and a hierarchical node transaction size associated with a given hierarchical level mapped to a given memory in which the given node is stored, optimizing run time performance of the walk.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 6, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Abhishek Dikshit
  • Method and apparatus for compiling search trees for processing request keys based on a key size supported by underlying processing elements
    Patent number: 9432284
    Abstract: A packet classification system, methods, and apparatus are provided for packet classification. A processor of a router coupled to a network compiles at least one search tree based on a rules set. The processor determines an x number of search phases needed to process an incoming key corresponding to the rules set, wherein the rules set includes a plurality of rules, where each of the plurality of rules includes an n number of rule fields and where the incoming key includes an n number of processing fields. The processor generates an x set of search trees, where each of the x set of search trees corresponds to a respective one of the x number of search phases. Also, the processor provides the x set of search trees to a search processor, where each of the x set of search trees is configured to process respective portions of the incoming key.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: August 30, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Kenneth Bullis
  • Merging independent writes, separating dependent and independent writes, and error roll back
    Patent number: 9430511
    Abstract: In an embodiment, a method of updating a memory with a plurality of memory lines, the memory storing a tree, a plurality of buckets, and a plurality of rules, includes maintaining a copy of the memory with a plurality of memory lines. The method further includes writing a plurality of changes to at least one of the tree, the plurality of buckets, and the plurality of rules to the copy. The method further includes determining whether each of the plurality of changes is an independent write or a dependent write. The method further includes merging independent writes to the same line of the copy. The method further includes transferring updates from the plurality of lines of the copy to the plurality of lines of the memory.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 30, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • SYSTEM AND METHOD FOR RULE MATCHING IN A PROCESSOR
    Publication number: 20160248739
    Abstract: In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding dimension for returning a match or nomatch. The system can further include a post processing block configured to analyze the matches or no matches returned from the DMEs and return a response based on the returned matches or nomatches.
    Type: Application
    Filed: May 3, 2016
    Publication date: August 25, 2016
    Inventors: Gregg A. Bouchard, Rajan Goyal, Gregory E. Lund
  • Method and apparatus for processing finite automata
    Patent number: 9426166
    Abstract: A method and corresponding apparatus for run time processing use a Deterministic Finite Automata (DFA) and Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload. A subpattern may be selected from each pattern in a set of one or more regular expression patterns based on at least one heuristic. The DFA may be generated from selected subpatterns from all patterns in the set, and at least one NFA may be generated for at least one pattern in the set, optimizing run time performance of the run time processing.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 23, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Method and apparatus for compilation of finite automata
    Patent number: 9426165
    Abstract: A method and corresponding apparatus are provided implementing run time processing using Deterministic Finite Automata (DFA) and Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload. A subpattern may be selected from each pattern in a set of one or more regular expression patterns based on at least one heuristic and a unified deterministic finite automata (DFA) may be generated using the subpatterns selected from all patterns in the set, and at least one non-deterministic finite automata (NFA) may be generated for at least one pattern in the set, optimizing run time performance of the run time processing.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 23, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Dikshit
  • Method and apparatus for processing of finite automata
    Patent number: 9419943
    Abstract: A method, and corresponding apparatus and system are provided for optimizing matching at least one regular expression pattern in an input stream by walking at least one finite automaton in a speculative manner. The speculative manner may include walking at least two nodes of a given finite automaton, of the at least one finite automaton, in parallel, with a segment, at a given offset within a payload of a packet in the input stream. The walking may include determining a match result for the segment, at the given offset within the payload, at each node of the at least two nodes. The walking may further include determining at least one subsequent action for walking the given finite automaton, based on an aggregation of each match result determined.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: August 16, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Abhishek Dikshit
  • Regular expression processing automaton
    Patent number: 9398033
    Abstract: A method and corresponding apparatus are provided implementing a stage one of run time processing using Deterministic Finite Automata (DFA) and implementing a stage two of run time processing using Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload, such as the payload portion of an Internet Protocol (IP) datagram, or an input stream.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 19, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Lakshmipathi Billa