Patents by Inventor Rajan Goyal

Rajan Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and Method to Traverse a Non-Deterministic Finite Automata (NFA) Graph Generated for Regular Expression Patterns with Advanced Features
    Publication number: 20150067836
    Abstract: In one embodiment, a method of walking an non-deterministic finite automata (NFA) graph representing a pattern includes extracting a node type and an element from a node of the NFA graph. The method further includes matching a segment of a payload for the element by matching the payload for the element at least zero times, the number of times based on the node type.
    Type: Application
    Filed: February 21, 2014
    Publication date: March 5, 2015
    Applicant: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Traversal With Arc Configuration Information
    Publication number: 20150066991
    Abstract: An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc may also include a nodal bit map including structural information of a node to which the valid arc points to. A walker process may utilize the nodal bit map to determine if a memory access is necessary. The nodal bit map reduces the number of external memory access and therefore reduces system run time.
    Type: Application
    Filed: October 17, 2014
    Publication date: March 5, 2015
    Inventor: Rajan Goyal
  • Generating a Non-Deterministic Finite Automata (NFA) Graph for Regular Expression Patterns with Advanced Features
    Publication number: 20150066927
    Abstract: In an embodiment, a method of compiling a pattern into a non-deterministic finite automata (NFA) graph includes examining the pattern for a plurality of elements and a plurality of node types. Each node type can correspond with an element. Each element of the pattern can be matched at least zero times. The method further includes generating a plurality of nodes of the NFA graph. Each of the plurality of nodes can be configured to match for one of the plurality of elements. The node can indicate the next node address in the NFA graph, a count value, and/or node type corresponding to the element. The node can also indicate the element representing a character, character class or string. The character can also be a value or a letter.
    Type: Application
    Filed: February 21, 2014
    Publication date: March 5, 2015
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Memory Management for Finite Automata Processing
    Publication number: 20150067200
    Abstract: Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite automation. The search context may be maintained in a manner that obviates overflow of the search context and obviating stalling of the push or pop operations to increase match performance.
    Type: Application
    Filed: April 14, 2014
    Publication date: March 5, 2015
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Timothy Toshio Nakada, Abhishek Dikshit
  • METHOD AND APPARATUS FOR COMPILATION OF FINITE AUTOMATA
    Publication number: 20150067776
    Abstract: A method and corresponding apparatus are provided implementing run time processing using Deterministic Finite Automata (DFA) and Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload. A subpattern may be selected from each pattern in a set of one or more regular expression patterns based on at least one heuristic and a unified deterministic finite automata (DFA) may be generated using the subpatterns selected from all patterns in the set, and at least one non-deterministic finite automata (NFA) may be generated for at least one pattern in the set, optimizing run time performance of the run time processing.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Dikshit
  • METHOD AND APPARATUS FOR PROCESSING FINITE AUTOMATA
    Publication number: 20150067863
    Abstract: A method and corresponding apparatus for run time processing use a Deterministic Finite Automata (DFA) and Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload. A subpattern may be selected from each pattern in a set of one or more regular expression patterns based on at least one heuristic. The DFA may be generated from selected subpatterns from all patterns in the set, and at least one NFA may be generated for at least one pattern in the set, optimizing run time performance of the run time processing.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Engine Architecture for Processing Finite Automata
    Publication number: 20150067123
    Abstract: An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at least one selected super-cluster is available as a resource pool of HPUs to the HNA scheduler for assignment of at least one HNA instruction to enable acceleration of a match of at least one regular expression pattern in an input stream received from a network.
    Type: Application
    Filed: July 8, 2014
    Publication date: March 5, 2015
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Gregg A. Bouchard, Timothy Toshio Nakada
  • On-chip memory (OCM) physical bank parallelism
    Patent number: 8966152
    Abstract: According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 24, 2015
    Assignee: Cavium, Inc.
    Inventors: Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Najeeb I. Ansari
  • Method and apparatus for managing processing thread migration between clusters within a processor
    Patent number: 8954700
    Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 10, 2015
    Assignee: Cavium, Inc.
    Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Satyanarayana Lakshmipathi Billa
  • Decision tree level merging
    Patent number: 8937954
    Abstract: A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. By merging levels of decision trees, the methods may produce wider, shallower trees that result in shorter search times and reduced memory requirements for storing the trees.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: January 20, 2015
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Kenneth A. Bullis
  • Packet classification
    Patent number: 8937952
    Abstract: A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. The methods may produce wider, shallower trees that result in shorter search times and reduced memory requirements for storing the trees.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: January 20, 2015
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Kenneth A. Bullis, Satyanarayana Lakshmipathi Billa
  • Identifying duplication in decision trees
    Patent number: 8934488
    Abstract: A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. By identifying duplication in decision trees, the methods may produce wider, shallower trees that result in shorter search times and reduced memory requirements for storing the trees.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: January 13, 2015
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Kenneth A. Bullis, Satyanarayana Lakshmipathi Billa
  • Phased bucket pre-fetch in a network processor
    Patent number: 8923306
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. Based on a prefetch status, a selection of the subset of rules are retrieved for rule matching. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Cavium, Inc.
    Inventors: Gregg A. Bouchard, Rajan Goyal
  • System and Method to Provide Non-Coherent Access to a Coherent Memory System
    Publication number: 20140372709
    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 18, 2014
    Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari
  • Method and Apparatus for a Virtual System on Chip
    Publication number: 20140359622
    Abstract: A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a method that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the method for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.
    Type: Application
    Filed: August 6, 2014
    Publication date: December 4, 2014
    Inventors: Muhammad Raghib Hussain, Rajan Goyal, Richard Kessler
  • Method and Apparatus for a Virtual System on Chip
    Publication number: 20140359621
    Abstract: A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.
    Type: Application
    Filed: August 6, 2014
    Publication date: December 4, 2014
    Inventors: Muhammad Raghib Hussain, Rajan Goyal, Richard Kessler
  • Deterministic finite automata graph traversal with nodal bit mapping
    Patent number: 8886680
    Abstract: An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc may also include a nodal bit map including structural information of a node to which the valid arc points to. A walker process may utilize the nodal bit map to determine if a memory access is necessary. The nodal bit map reduces the number of external memory access and therefore reduces system run time.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Cavium, Inc.
    Inventor: Rajan Goyal
  • Intelligent Graph Walking
    Publication number: 20140324900
    Abstract: An apparatus, and corresponding method, for performing a search for a match of at least one expression in an input stream is presented. A graph including a number of interconnected nodes is generated. A compiler may assign at least one starting node and at least one ending node. The starting node includes a location table with node position information of an ending node and a sub-string value associated with the ending node. Using the node position information and a string comparison function, intermediate nodes located between the starting and ending nodes may be bypassed. The node bypassing may reduce the number of memory accesses required to read the graph.
    Type: Application
    Filed: July 7, 2014
    Publication date: October 30, 2014
    Inventors: Muhammad Raghib Hussain, Rajan Goyal, Imran Badr
  • System and method to reduce memory access latencies using selective replication across multiple memory ports
    Patent number: 8850101
    Abstract: In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Cavium, Inc.
    Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler
  • System and method to provide non-coherent access to a coherent memory system
    Patent number: 8850125
    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: September 30, 2014
    Assignee: Cavium, Inc.
    Inventors: Jeffrey Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari