Abstract: An embodiment for modifying the contents of a revision identification register includes a revision identification register that is both readable and writable (the contents of the revision identification register are modifiable). A revision identification modification bit is also included. The contents of the revision identification register are only modifiable when the revision identification modification bit is set to indicate that writes to the revision identification register will be accepted.

Abstract: Embodiments of the present invention provide for an ACPI Non-Volatile Sleeping (NVS) memory region that is allocated and defined so that a system BIOS can save CMOS based memory content at the ACPI NVS memory region during power on system test (POST). The ACPI NVS memory region and it's associated content, is accessible to both OS and non-OS software during runtime execution.

Abstract: In one aspect, a method is disclosed. The method includes trapping initializing data of a first interrupt type to a first interrupt controller, re-routing the initializing data of the first interrupt type to a second interrupt controller, and configuring the second interrupt controller to manage interrupt of the first interrupt type.

Abstract: Embodiments of the present invention provide for implementation of data transfers in an efficient manner. The 48-bit LBA mechanism requires two sets of I/O writes to IDE registers on primary channel or secondary channel. The two sets of I/O writes to the primary or secondary channel registers are performed by setting a status register to a first or second state appropriately depending on the data. Embodiments of the present invention provide a single set of writes to I/O registers when the size of the data transfer is equal to or below a threshold value.

Abstract: A first driver bypasses execution of a transaction descriptor that causes a non-maskable interrupt (NMI) when executed by a host controller while under control of a second driver. The transaction descriptor is pointed to by an entry in a frame list. The host controller has a plurality of host controller registers including a frame list base address register defining a base address of the frame list and a frame number register addressing the entry.

Abstract: Methods, apparatus and machine readable medium are described in which BIOS initialization code divides one or more storage devices into two or more portions. Further, a BIOS device handler may use the portions of the divided storage devices to implement a storage array that provides attributes of one or more RAID levels.

Abstract: Embodiments of the present invention provide for a pre-operating system (OS) routine that facilitates detection of configuration changes in the system. In particular, the pre-OS routine stores a dynamic configuration list of devices, which is accessed when a configuration change, such as adding or removing a device on the platform, is detected. An authentication routine is enforced prior to giving the user access to resources on the platform. Unauthorized access to the platform is prohibited.

Abstract: Embodiments of the present invention provide for an ACPI Non-Volatile Sleeping (NVS) memory region that is allocated and defined so that a system BIOS can save CMOS based memory content at the ACPI NVS memory region during power on system test (POST). The ACPI NVS memory region and it's associated content, is accessible to both OS and non-OS software during runtime execution.

Abstract: System and method for device support. The system may comprise a processor, a memory, a device controller and a basic input-output system (BIOS). The memory may be mapped according to a predetermined specification, such as the Advanced Configuration and Power Interface (ACPI) specification. A device support component in the BIOS uses a portion of a defined region of the memory, such as the non-volatile sleeping (NVS) memory region, to maintain device data for a device. A method involves providing the software component in the BIOS. The software component maps the memory, reserving a portion of the defined region of the memory to maintain a plurality of device data regarding the device controller, and provides support for at least one device utilizing the portion of the defined region of the memory. The system and method may be used with Universal Serial Bus (USB) devices and controllers, as well as with secondary graphics adapters.

Abstract: METHOD AND APPARATUS FOR HANDLING DATA TRANSFERS Embodiments of the present invention provide for implementation of data transfers in an efficient manner. The 48-bit LBA mechanism requires two sets of I/O writes to IDE registers on primary channel or secondary channel. The two sets of I/O writes to the primary or secondary channel registers are performed by setting a status register to a first or second state appropriately depending on the data. Embodiments of the present invention provide a single set of writes to I/O registers when the size of the data transfer is equal to or below a threshold value.

Abstract: An ACPI (Non-Volatile Sleeping) NVS memory region is allocated and defined so that a system BIOS can allocate a placeholder for the different parameters that are passed from the ACPI ASL code to the system management mode (SMM) handler for execution of real mode calls. The different parameters will be updated by runtime ACPI ASL code depending on what needs to be passed to the SMM handler. The SMM handler invokes appropriate calls based on retrieving of different parameters in the ACPI NVS memory region that have been passed from the ACPI ASL code.

Abstract: Embodiments of the present invention provide for executing real-mode interrupts from within an extended SMRAM handler. If there is a need to make a real-mode call from the extended SMRAM handler, control is transferred to a compatible SMRAM region and appropriate calls to the real-mode calls are executed from within the compatible SMRAM region. The call from the extended SMRAM handler code to the compatible SMRAM code switches the processor from protected mode to real-mode. After the real-mode call is complete, control is returned to the compatible SMRAM handler. The processor is placed back into protected mode and control transferred back to the extended SMRAM handler code.

Abstract: Embodiments of the present invention provide for generation of SMI from ACPI ASL control method code to execute complex tasks including, but not limited to, transferring or searching through large amounts of data dynamically. Instead of executing certain tasks using limited ASL functionality, an SMI is generated in an ASL code execution path to enable usage of a CPU instruction set accessible to the SMM handler. In particular, an ACPI operation region is defined for an I/O address location capable of triggering an SMI. An ACPI control method accesses the SMI generation I/O address location to generate an SMI during ASL code execution when a predefined complex task is encountered, thus enabling the SMI handler code to advantageously execute the complex task.

Abstract: Embodiments of the present invention provide for executing real-mode interrupts from within an extended SMRAM handler. If there is a need to make a real-mode call from the extended SMRAM handler, control is transferred to a compatible SMRAM region and appropriate calls to the real-mode calls are executed from within the compatible SMRAM region. The call from the extended SMRAM handler code to the compatible SMRAM code switches the processor from protected mode to real-mode. After the real-mode call is complete, control is returned to the compatible SMRAM handler. The processor is placed back into protected mode and control transferred back to the extended SMRAM handler code.

Abstract: An embodiment for modifying the contents of a revision identification register includes a revision identification register that is both readable and writable (the contents of the revision identification register are modifiable). A revision identification modification bit is also included. The contents of the revision identification register are only modifiable when the revision identification modification bit is set to indicate that writes to the revision identification register will be accepted.

Abstract: A technique for computer initialization with caching includes enabling at least one cache memory and then copying an option BIOS from a first memory to a PAM (Programmable Attribute Map) main memory area, the copying including executing a cache-line fill to the at least one cache memory. Initialization is then performed by providing control to the option BIOS, the execution being performed substantially from the at least one cache memory. Processor MTRRs(Memory Type Range Registers) for the PAM memory area may be programmed as write-back. The at least one cache memory may be at least one of L1 and L2 processor cache memories. The first memory may be a flash memory or a ROM (Read Only Memory). The at least one cache memory may be flushed upon completion of the option BIOS execution.

Abstract: A computer system is provided with a single processor equipped to serve as multiple logical processors. The computer system comprises a host chipset connected to the processor; PCI devices connected to the host chipset, via a PCI bus; and a main storage connected to the host chipset and arranged to store an operating system (OS) and contain a basic input/output system (system BIOS) configured to execute multiple pre-boot tasks, including memory initialization and PCI bus initialization concurrently, on the processor which serve as multiple logical processors before passing control to the operating system (OS).

Abstract: System and method for device support. The system may comprise a processor, a memory, a device controller and a basic input-output system (BIOS). The memory may be mapped according to a predetermined specification, such as the Advanced Configuration and Power Interface (ACPI) specification. A device support component in the BIOS uses a portion of a defined region of the memory, such as the non-volatile sleeping (NVS) memory region, to maintain device data for a device. A method involves providing the software component in the BIOS. The software component maps the memory, reserving a portion of the defined region of the memory to maintain a plurality of device data regarding the device controller, and provides support for at least one device utilizing the portion of the defined region of the memory. The system and method may be used with Universal Serial Bus (USB) devices and controllers, as well as with secondary graphics adapters.

Abstract: A first driver bypasses execution of a transaction descriptor that causes a non-maskable interrupt (NMI) when executed by a host controller while under control of a second driver. The transaction descriptor is pointed to by an entry in a frame list. The host controller has a plurality of host controller registers including a frame list base address register defining a base address of the frame list and a frame number register addressing the entry.

Abstract: System and method for external bus device support. The system comprises a processor, a memory, one or more external bus controllers and a basic input-output system (BIOS). The BIOS contains an external bus support component to cause a periodic interrupt to be generated and to provide support for external bus enabled devices responsive to the periodic interrupt. The method comprises obtaining a portion of the memory to be used to maintain a plurality of external bus device data; causing an interrupt to be periodically generated; and handling input produced by external bus enabled devices using the portion of the memory. The interrupt may be a system management interrupt (SMI) of the 32-bit Intel Architecture (IA-32). The external bus controller may be a Universal Serial Bus (USB) host controller, the external bus devices may be USB devices, and the external bus support component may be a USB support component.