Abstract: An apparatus to facilitate data parallel programming-based transparent transfer across heterogeneous devices is disclosed. The apparatus includes a processor to: identify a change in device status that triggers a device transfer process from an original device, wherein the original device is associated with a queue of an application program of a data parallel programming runtime; identify a new device that is compatible with the original device; migrate at least one of a state or data of the original device to the new device; logically map, without user intervention, the queue to the new device in the data parallel programming runtime; and initiate execution of the application program on the new device using the queue.

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.

Abstract: An apparatus to facilitate incremental just-in-time (JIT) performance refinement for programmable logic device offload is disclosed. The apparatus includes a processor to: initiate multiple just-in-time (JIT) compilation iterations of an application; program a first architecture of a first compilation of the multiple JIT compilation iterations to a programmable logic device and execute the application on the first architecture, wherein the first compilation comprises a faster compilation time amongst the multiple JIT compilation iterations; identify a hotspot; determine that a second compilation of the multiple JIT compilation iterations is complete, wherein the second compilation comprises a slower compilation time than the first compilation; and program a second architecture of the second compilation of the multiple JIT compilation iterations to the programmable logic device and execute the application on the second architecture.

Abstract: An apparatus to facilitate data parallel programming task graph optimization through device telemetry is disclosed. The apparatus includes a processor to: receive, from a compiler, compiled code generated from source code of an application, the compiled code to support a workload of the application; generate a task graph of the application using the compiled code, the task graph to represent at least one of a relationship or dependency of the compiled code; receive runtime telemetry data corresponding to execution of the compiled code on the one or more accelerator devices; identify one or more scheduling optimizations for the one or more accelerator devices based on the task graph and the received telemetry data; and provide a scheduling command to cause the one or more scheduling optimizations to be implemented in the one or more accelerator devices.

Abstract: An apparatus to facilitate clock gating and clock scaling based on runtime application task graph information is disclosed. The apparatus includes a processor to: receive, from a compiler, a bitstream generated from code of an application, the bitstream related to a workload of the application; generate a task graph of the application using at least part of the bitstream, the task graph to represent one of a relationship and dependency of the code; program the bitstream to an accelerator device, wherein the bitstream to configure the accelerator device to support the workload of the application; execute one or more kernels of the code using the accelerator device; identify one or more optimizations for the accelerator device based on the task graph of the application; and transmit a command to cause the one or more optimizations to be implemented in the at least one region of the accelerator device.

Abstract: Methods, apparatus, systems, and articles of manufacture to perform platform agnostic control of a display using a hardware agent are disclosed. An example apparatus includes memory; instructions in the apparatus; and hardware agent to execute the instructions to: obtain a battery level; and during a boot protocol: determine that the battery level is below a threshold; determine a panel brightness based on the battery level, the panel brightness being less than a maximum brightness of the panel; and transmit instructions to a driver corresponding to the panel to cause the panel to operate at the determined amount of brightness.

Abstract: A disclosed example apparatus includes memory; and at least one processor to execute first instructions, the first instructions obtained from first encrypted firmware, the at least one processor to: encrypt handoff data with an original equipment manufacturer key to generate encrypted handoff data; decrypt second encrypted firmware based on the original equipment manufacturer key to generate second instructions; and provide access to the encrypted handoff data to the second instructions, the second instructions to perform initialization of a computer based on the handoff data obtained from the encrypted handoff data.

Abstract: Methods, apparatus, systems and articles of manufacture to dynamically control devices based on distributed data are disclosed. An example apparatus includes a comparator to compare a first measurement measured by a first peer device to a second measurement, the second measurement being measured locally by the apparatus; and an operation adjuster to, when the comparison satisfies a threshold, adjust a measurement protocol of the first peer device.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to support post-manufacturing firmware extensions on computing platforms. An example non-transitory computer readable storage medium comprising instructions that, when executed, cause one or more processors to at least: based on a soft strap status indicator stored in a serial peripheral interface (SPI) memory, extract a silicon initialization code profile from the SPI memory and initialize the processor based on the silicon initialization code extension profile.

Abstract: A system includes a host processor operable to communicate with a remote requestor to perform operations for attesting a trusted system. The system also includes a hardware acceleration coprocessor coupled to the host processor. The host processor is further operable to offload at least some of the operations onto the hardware acceleration coprocessor to free up processing power on the host processor.

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.

Abstract: Methods, apparatuses and system provide for technology that interleaves a plurality of verification commands with a plurality of copy commands in a command buffer, wherein each copy command includes a message authentication code (MAC) derived from a master session key, wherein one or more of the plurality of verification commands corresponds to a copy command in the plurality of copy commands, and wherein a verification command at an end of the command buffer corresponds to contents of the command buffer. The technology may also add a MAC generation command to the command buffer, wherein the MAC generation command references an address of a compute result.

Abstract: Methods, apparatus, systems, and articles of manufacture for data enhanced automated model generation are disclosed. Example instructions, when executed, cause at least one processor to access a request to generate a machine learning model to perform a selected task, generate task knowledge based on a previously generated machine learning model, create a search space based on the task knowledge, and generate a machine learning model using neural architecture search, the neural architecture search beginning based on the search space.

Abstract: Methods, apparatus, systems, and articles of manufacture for dynamic XPU hardware-aware deep learning model management are disclosed. An example method includes extracting a plurality of models from a dataset, respective ones of the plurality of models optimized for a selected quality of service (QoS) objective of a plurality of QoS objectives, identifying a plurality of feature differences between respective ones of the plurality of models, and identifying a plurality of feature similarities between respective ones of the plurality of models.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for composable machine learning compute nodes. An example apparatus includes interface circuitry to receive a workload, instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to generate a first configuration of one or more machine-learning models based on a workload, generate a second configuration of hardware, determine an evaluation parameter based on an execution of the workload, the execution of the workload based on the first configuration and the second configuration, and, in response to the evaluation parameter satisfying a threshold, execute the one or more machine-learning models in the first configuration on the hardware in the second configuration, the one or more machine-learning models and the hardware to execute the workload.

Abstract: Methods, apparatus, and articles of manufacture to conditionally activate a big core in a computing system are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing instructions according to the request; when the two or more processing devices are available and capable: split the instructions into first sub-instructions and second sub-instructions; provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices; and generate an output by combining a first output of the first processing device and a second output of the second processing device.

Abstract: A drone includes technology for tracking controllers. A controller registration module (CRM) in the drone enables the drone to receive a first controller identifier from a first remote device. In response to receiving the first controller identifier, the CRM registers the first remote device as the current controller for the drone. Registering comprises adding the first controller identifier to a drone control registration record (DCRR) in the drone. Also, the DCRR is added to a block chain in remote storage. The CRM then receives a second controller identifier from a second remote device. In response, the CRM registers the second remote device as the current controller. Registering comprises creating an updated DCRR that identifies the second controller as the current controller. The updated DCRR is then added to the block chain. Other embodiments are described and claimed.

Abstract: Disclosed herein are distributed ledger systems and methods for efficiently creating and updating a query optimized distributed ledger. In particular, the present disclosure introduces methods and apparatuses for efficiently updating indexes when new blocks are added to the distributed ledger by using snapshots of data and appending new snapshot tables and indexes to previous snapshot tables and indexes.

Abstract: A system can dynamically apply compression to data storage for workloads based on how the compression affects the performance for the workloads. The system can track a service level indicator (SLI) during runtime of a workload and dynamically change a level of compression for the workload based on the SLI. The system can track the SLI to increase compression for the workload while maintaining a performance minimum specified in a service level agreement (SLA) for the workload.

Abstract: Systems, apparatuses, methods, and computer-readable media, are provided for providing connectivity-based and/or connectivity-considered routing with supplemental wireless connections in driving assistance-related activities. Embodiments may be relevant to multi-access edge computing (MEC) and Automotive Edge Computing Consortium (AECC) technologies. Other embodiments may be described and/or claimed.