Patents by Inventor Ralph G. Whitten
Ralph G. Whitten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6940093Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: GrantFiled: December 29, 2000Date of Patent: September 6, 2005Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6825052Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.Type: GrantFiled: December 11, 2002Date of Patent: November 30, 2004Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Publication number: 20040148122Abstract: Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.Type: ApplicationFiled: January 12, 2004Publication date: July 29, 2004Applicant: FormFactor, Inc.Inventors: Ralph G. Whitten, Benjamin N. Eldridge
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Patent number: 6724209Abstract: Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.Type: GrantFiled: April 13, 2000Date of Patent: April 20, 2004Inventors: Ralph G. Whitten, Benjamin N. Eldridge
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Patent number: 6690185Abstract: A method of fabricating a large contactor (62) is provided wherein one or more contactor units (78) are mounted on a support substrate (74) such that contact elements (80) attached to the contactor units are suitably aligned. In this manner, a large area contactor can be prepared using a plurality of smaller contactor units. Preferably the contact elements on the plurality of contactor units are coplanar across the contactor units. This is particularly advantageous for making a large contactor for probing semiconductor devices on a wafer. This also can be useful for making a contactor capable of contacting devices across an entire semiconductor wafer. In one embodiment, the contactor units self-align during reflow of a joining material such as solder balls (134) or other reflowable material interconnecting the contactor units and the support substrate.Type: GrantFiled: November 19, 1998Date of Patent: February 10, 2004Assignee: FormFactor, Inc.Inventors: Igor Y Khandros, David V. Pedersen, Ralph G. Whitten
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Publication number: 20040004216Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.Type: ApplicationFiled: December 11, 2002Publication date: January 8, 2004Applicant: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6621260Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: GrantFiled: December 29, 2000Date of Patent: September 16, 2003Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6603324Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: GrantFiled: December 29, 2000Date of Patent: August 5, 2003Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6597187Abstract: An integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g.Type: GrantFiled: December 29, 2000Date of Patent: July 22, 2003Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6551844Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.Type: GrantFiled: December 31, 1998Date of Patent: April 22, 2003Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6476630Abstract: Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.Type: GrantFiled: May 9, 2000Date of Patent: November 5, 2002Assignee: FormFactor, Inc.Inventors: Ralph G. Whitten, Benjamin N. Eldridge
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Patent number: 6456099Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: GrantFiled: December 31, 1998Date of Patent: September 24, 2002Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6429029Abstract: One embodiment of the present invention concerns a design methodology for generating a test die for a product die including the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die.Type: GrantFiled: December 31, 1998Date of Patent: August 6, 2002Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Publication number: 20010052786Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: ApplicationFiled: December 29, 2000Publication date: December 20, 2001Applicant: FormFactor, Inc. a Delaware coporationInventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Publication number: 20010020743Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: ApplicationFiled: December 29, 2000Publication date: September 13, 2001Applicant: FormFactor. Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Publication number: 20010020747Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: ApplicationFiled: December 29, 2000Publication date: September 13, 2001Applicant: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Publication number: 20010015773Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.Type: ApplicationFiled: December 29, 2000Publication date: August 23, 2001Applicant: FormFactor, Inc., a Delaware corporationInventors: Benjamin N. Eldridge, Igor Y. Khandros, David V. Pedersen, Ralph G. Whitten
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Patent number: 6150199Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.Type: GrantFiled: September 27, 1999Date of Patent: November 21, 2000Assignee: QuickLogic CorporationInventors: Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas, Hua-Thye Chua, Andrew K. Chan, John M. Birkner
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Patent number: 5989943Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.Type: GrantFiled: December 8, 1989Date of Patent: November 23, 1999Assignee: QuickLogic CorporationInventors: Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas, Hua-Thye Chua, Andrew K. Chan, John M. Birkner
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Patent number: 5780919Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.Type: GrantFiled: May 21, 1996Date of Patent: July 14, 1998Assignee: QuickLogic CorporationInventors: Hua-Thye Chua, Andrew K. Chan, John M. Birkner, Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas