Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.

Abstract: A deformable grating aparatus for modulating light is made by forming an insulating layer on a substrate, forming a first conductive layer on the insulating layer and then forming a sacrificial layer thereon. The sacrificial layer and the first conducting layer are then etched to define bit lines and busses to bonding pads. Then a layer of resilient material is formed onto the etched layers and a reflective conducting layer is formed on the resilient layer. A dielectric layer is deposited on the reflective conducting layer. The dielectric layer, the reflective conducting layer, the resilient layer and the sacrificial layer are all then etched to form a grating including a plurality of parallel elements. Thereafter the sacrificial layer is removed below the parallel elements, to suspend the parallel elements over the first conducting layer. The surface is treated to prevent the grating from adhering to the first conducting layer.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract: A user-programmable interconnect device includes a first lower electrode comprising a conductive material. A layer of dielectric material is disposed over the top surface of the lower conductor. An antifuse material, such as one or more layers of a dielectric material, amorphous silicon, or combinations of such materials, is located in an aperture in the dielectric material where the interconnect element of the present invention is to be formed. A second, upper electrode of conductive material is formed over the top of the antifuse material. A portion of the upper electrode located immediately above the antifuse material is fabricated as a fuse material. A passivation layer covers the second electrode and may have an aperture located therein at a location immediately above the antifuse and fuse material. Electrical connections to circuitry incorporating the interconnect element of the present invention are made to the lower and upper electrodes.

Abstract: An interconnection matrix configured according to the present invention includes a plurality of conductors disposed on a substrate which may contain an integrated circuit. A first group of the conductors are directly connected to I/O pins provided on the substrate. A second group of the conductors are internal to the substrate. A plurality of programmable elements are disposed on the substrate and are connected between selected ones of the first and second groups of conductors. By selectively programming the antifuse elements, a user may configure the conductors into a custom interconnect pattern. Means are provided to place each conductor in the second group of internal segmented conductors at a selected voltage during programming of the interconnect architecture of the present invention. The antifuses in a selected circuit path between two I/O pads are all initially programmed at an appropriate programming voltage utilizing a low current.

Abstract: A first passive ESD protection device for an electronic component in a microcircuit includes a fuse element shunting the component to be protected and includes a passive programming path from the outside of the microcircuit to the fuse element. A second passive ESD protection device is deactivatable and reactivatable and includes a first fuse element shunted by a second fuse element in series with a first antifuse element. Shunting the second fuse element with a third fuse element in series with a second antifuse element permits a second deactivation and reactivation to be performed. Additional deactivation/reactivation cycles may be permitted by providing additional series combinations of fuse elements and antifuse elements shunting the preceding fuse element. Combinations of the passive protection device and dual elements comprise ESD protection schemes which may be deactivated and activated multiple times.

Abstract: A fusible link structure and method of making the same for use in integrated circuit structures is provided in which the fusible link comprises, in one embodiment, an alloy of platinum and silicon. The preferred alloy comprises the eutectic mixture having approximately 23 atomic percent silicon. Electrical connections to the fusible link are preferably provided by a layer of aluminum on a layer of material, preferably an alloy of titanium and tungsten wherein the titanium and tungsten alloy is disposed between the fusible link and the aluminum layer, and serves as a diffusion barrier for preventing diffusion of the aluminum into the fusible link. In a preferred embodiment, a fusible link is deposited on a relatively thick dielectric layer, preferably more than 10,000 .ANG. thick, having a relatively low thermal conductivity.