Patents by Inventor Rebecca D. Mih
Rebecca D. Mih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8815475Abstract: A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.Type: GrantFiled: January 7, 2013Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Patent number: 8439728Abstract: A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.Type: GrantFiled: October 21, 2011Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Publication number: 20120040277Abstract: A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.Type: ApplicationFiled: October 21, 2011Publication date: February 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Patent number: 8110321Abstract: A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.Type: GrantFiled: May 16, 2007Date of Patent: February 7, 2012Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Publication number: 20080286660Abstract: A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.Type: ApplicationFiled: May 16, 2007Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Patent number: 6504207Abstract: A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.Type: GrantFiled: June 30, 2000Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Bomy A. Chen, Jay G. Harrington, Kevin M. Houlihan, Dennis Hoyniak, Chung Hon Lam, Hyun Koo Lee, Rebecca D. Mih, Jed H. Rankin
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Patent number: 6448629Abstract: A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.Type: GrantFiled: July 29, 1999Date of Patent: September 10, 2002Assignee: International Business Machines CorporationInventors: Rebecca D. Mih, Kevin S. Petrarca
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Patent number: 6429522Abstract: A multi-layer semiconductor circuit comprising a plurality of conductive lines having air as a dielectric between the sides of the conductive lines in a first layer and having a structurally supportive non-metal cap layer at least partially covering the top of the conductive lines in the first layer and separating the air dielectric and conductive lines in the first layer from any subsequent layers. In a multi-layer semiconductor circuit with a plurality of conductive lines, at least the top, the bottom, and the opposite sides of each line are encapsulated by an adhesion-promotion barrier layer, and the barrier layer on the top of each conductive line has an upper surface that is flush with (a) a planar lower surface of a cap layer over the barrier layer, (b) a planar upper surface of a dielectric layer between the conductive lines, or (c) a combination thereof. The dielectric layer between the conductive lines may be air.Type: GrantFiled: December 20, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Rebecca D. Mih
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Publication number: 20020076621Abstract: A photolithographic mask having a primary photolithographic mask having a pattern thereon, the pattern comprising at least two portions, each portion requiring an individual optimal energy to image the pattern, each optimal energy of each portion dissimilar to at least one of the at least two portions and a secondary photolithographic mask on at least one portion of the primary mask, the secondary mask capable of attenuating the light on at least one of the at least two portions such that the optimal energy required to image the pattern on the at least one portion is similar to another of the at least two portions.Type: ApplicationFiled: December 22, 1999Publication date: June 20, 2002Inventors: REBECCA D. MIH, KEVIN S. PETRARCA, DONALD C. WHEELER
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Patent number: 6407396Abstract: A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture.Type: GrantFiled: June 24, 1999Date of Patent: June 18, 2002Assignee: International Business Machines CorporationInventors: Rebecca D. Mih, Eric P. Solecky, Donald C. Wheeler
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Patent number: 6391703Abstract: A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.Type: GrantFiled: June 28, 2001Date of Patent: May 21, 2002Assignee: International Business Machines CorporationInventors: Nivo Rovedo, Chung H. Lam, Rebecca D. Mih
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Publication number: 20020048707Abstract: A photolithographic method, involving the illuminating of a mask with ray angles of light, the illumination passing through an annular aperture prior to contacting the mask, the illumination passing through to the mask capable of imaging the surface below, the mask comprising a primary photolithographic mask having a pattern thereon, the pattern comprising at least two portions, each portion requiring an individual optimal energy to image the pattern, each optimal energy of each portion dissimilar to at least one of the at least two portions;Type: ApplicationFiled: December 22, 1999Publication date: April 25, 2002Inventors: REBECCA D. MIH, KEVIN S. PETRARCA, DONALD C. WHEELER
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Publication number: 20010050414Abstract: A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.Type: ApplicationFiled: July 29, 1999Publication date: December 13, 2001Inventors: REBECCA D. MIH, KEVIN S. PETRARCA
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Patent number: 6326275Abstract: A DRAM memory cell having a trench capacitor includes a vertical pass transistor formed in the top of the trench in a process that forms a doped poly protective layer on the upper sidewalls above a sacrificial intrinsic poly spacer layer, the doped poly protecting the sidewalls while the intrinsic poly spacer layer is removed and replaced with a conductive strap layer that both forms a strap from the capacitor electrode and serves as a source of dopant to form a transistor electrode in the silicon substrate; the protective layer and the upper portion of the strap material being removed simultaneously so that no extra step is required; after which the trench walls are oxidized to form the transistor gate dielectric and conductive material is deposited to form the wordline and the gates for the vertical transistors simultaneously.Type: GrantFiled: April 24, 2000Date of Patent: December 4, 2001Assignee: International Business Machines CorporationInventors: Jay G. Harrington, David V. Horak, Kevin M. Houlihan, Chung Hon Lam, Rebecca D. Mih
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Patent number: 6284574Abstract: A structure and process are described for facilitating the conduction of heat away from a semiconductor device. Thermally conductive planes and columns are incorporated within the back-end structure and around the interconnect outside the chip. A thermally conductive plane is formed by forming a first insulating layer on an underlying layer of the device; forming a recess in the insulating layer; filling the recess with a thermally conductive material to form a lateral heat-dissipating layer; planarizing the heat-dissipating layer to make the top surface thereof coplanar with the unrecessed portion of the insulating layer; and forming a second insulating layer on the first insulating layer and the heat-dissipating layer, thereby embedding the heat-dissipating layer between the first and second insulating layers. The heat-dissipating layer is electrically isolated from the underlying layer of the device, and preferably is electrically grounded.Type: GrantFiled: January 4, 1999Date of Patent: September 4, 2001Assignee: International Business Machines CorporationInventors: Kevin Shawn Petrarca, Sarah Knickerbocker, Joyce C. Liu, Rebecca D. Mih
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Publication number: 20010016411Abstract: A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.Type: ApplicationFiled: December 20, 2000Publication date: August 23, 2001Inventors: Kevin S. Petrarca, Rebecca D. Mih
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Patent number: 6268261Abstract: A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.Type: GrantFiled: November 3, 1998Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Rebecca D. Mih
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Patent number: 6258732Abstract: An organic dielectric material is patterned on a substrate in a process utilizing a patterned resist which contains a metalloid or metallic element at the time of pattern transfer to the organic dielectric layer. The organic dielectric layer is preferably patterned using an oxygen etching process, most preferably oxygen reactive ion etching. The process advantageously avoids the need for a hard mask.Type: GrantFiled: February 4, 1999Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Rebecca D. Mih, Kevin S. Petrarca
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Patent number: 6228745Abstract: Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.Type: GrantFiled: December 13, 1999Date of Patent: May 8, 2001Assignee: International Business Machines CorporationInventors: Donald C. Wheeler, Louis L. Hsu, Jack A. Mandelman, Rebecca D. Mih
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Patent number: 6132940Abstract: A method of making at least one feature on an object having an upper surface, comprising the steps of:1. applying a layer of a photoresist having an initial thickness to the upper surface;2. exposing the layer of photoresist to a first dosage of light having a first intensity for a first predetermined period of time, such that at least a portion of the upper surface has a thickness that is at most equal to the initial thickness; and3. exposing the layer of photoresist to a second dosage of light having a second intensity for a second predetermined period of time, such that at least a subset of the portion of the upper surface exposed by the first dosage of light is exposed by the second dosage of light.Type: GrantFiled: December 16, 1998Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Rebecca D. Mih, Franz X. Zach