Abstract: A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap is repurposed to generate, along with the main tap, the main PAM-4 signaling levels. At least one PAM-2 FFE tap is repurposed to apply FFE in the PAM-4 mode.

Abstract: A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap is repurposed to generate, along with the main tap, the main PAM-4 signaling levels. At least one PAM-2 FFE tap is repurposed to apply FFE in the PAM-4 mode.

Abstract: A receiver frontend having a high-frequency AC-coupled path in parallel to a low-frequency feed-forward path for baseline correction. The low-frequency path blocks the DC common-mode voltage of the input differential signal pair, but passes low-frequency differential signal components (e.g., long strings of a single value, or disparities in the number of 1's and 0's over a long period of time.) The low-frequency path can include a passive network for level shifting and extending the range of acceptable common-mode input voltages. The low-frequency path can also include a differential (e.g., transconductance) amplifier to isolate the common-mode input voltage from the output of the baseline wander correction circuit.

Abstract: A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap is repurposed to generate, along with the main tap, the main PAM-4 signaling levels. At least one PAM-2 FFE tap is repurposed to apply FFE in the PAM-4 mode.

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: The common-mode input voltage of a common-gate input amplifier receiving a differential signal is set in an open-loop manner by basing the bias current and/or source load impedances of the common-gate amplifier on a transmitter bias current and driving impedance. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a closed-loop manner using a feedback loop having a captured target voltage compared to the common-mode input voltage at a node of the amplifier. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a continuous time closed loop manner by sending a reference current through resistances that are multiples of a resistance used to generate the reference current.

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: The disclosed embodiments relate to a digital phase-locked loop (PLL) with dynamic gain control. This digital PLL includes a phase detector which receives a reference signal and a feedback signal as inputs and produces an output signal comprising up/down values. It also includes a digital loop filter which receives the phase-detector output signal as an input and produces an M-bit output signal. This digital loop filter is associated with a loop-parameter control unit (LPCU) which dynamically generates loop-filter parameters for the digital loop filter based on an observed pattern of up/down values from the phase-detector output over a specified period of time. A digitally controlled oscillator (DCO) receives the loop-filter output signal and produces a PLL output signal. Finally, a feedback path returns the PLL output signal to the phase detector.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: The disclosed embodiments relate to a digital phase-locked loop (PLL) with dynamic gain control. This digital PLL includes a phase detector which receives a reference signal and a feedback signal as inputs and produces an output signal comprising up/down values. It also includes a digital loop filter which receives the phase-detector output signal as an input and produces an M-bit output signal. This digital loop filter is associated with a loop-parameter control unit (LPCU) which dynamically generates loop-filter parameters for the digital loop filter based on an observed pattern of up/down values from the phase-detector output over a specified period of time. A digitally controlled oscillator (DCO) receives the loop-filter output signal and produces a PLL output signal. Finally, a feedback path returns the PLL output signal to the phase detector.

Abstract: A phase-locked loop is placed in a low-power mode. The input to the variable-frequency oscillator is stored before the low-power mode is entered. Then, when the phase-locked loop is awakened, the previous input to variable-frequency oscillator is held at the input to the variable-frequency oscillator. While the input to variable-frequency oscillator is being held, the phase of the feedback signal is calibrated to the reference signal. Once the phase difference between the feedback signal and the reference signal is minimized, the normal feedback operation of the phase-locked loop is enabled.