Abstract: An original composite eye diagram is reformulated by deliberately re-aligning its component eye diagrams according to some appropriate standard. This ‘forced-alignment’ shifts the components in one or both of the time and voltage axes. Notice is taken of the shift(s) for each channel, and that shift data is appended to the data structures for the original components. The content of the data structure can be read in its original form, or, read and force-aligned. A force-aligned composite eye diagram created from the re-aligned components can then be displayed, investigated and evaluated with any of the existing tools that are used to analyze eye diagrams, simply by instructing the process that reads a component eye diagram data structure to reform that component as it is being read. Automatic forced-alignment of the component eye diagrams involves two steps. First, for each component eye diagram some specified property an ‘earmark’ having a (time, voltage) value is measured.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).

Abstract: A sampling transition-through-a-selected-voltage-detector sets two latches to different values when an input signal comparator referenced to the selected voltage transitions during a sample interval: at the beginning of the sample interval one latch receives one comparison value while at the end of the sample interval the other latch receives an opposite comparison value. A difference (XOR) in latched values for the transition detection latches indicates a transition through the selected voltage during the sample interval. A solution to the problem of such a transition-through-a-selected-voltage detection mechanism's insensitivity to steady state voltages may be solved by including an additional latch that is set by a second input signal comparator whose reference voltage is offset slightly from that used to detect transitions through the selected voltage, and that is also clocked at the start of the sample interval. Thus there are two latches clocked at the start of the sample interval.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).

Abstract: An eye diagram analyzer assigns a plurality of SUT data signals to be members of a labeled group of channels. There may be a plurality of such groups. In addition to mere superposition in an (X, Y) display space of the various i-many (X, Y)-valued pixels for individual component eye diagrams associated with that group, other measured data for those pixels within a group can be merged in various different modes to produce corresponding composite eye diagram presentations. E.g., in a Normalized Signal Density Mode the number of hits at each trial measurement point is summed over all channels in the group, and then divided by the total number of clock cycles measured for the ith measurement point in that group to produce a density Di associated with the corresponding ith pixel: (Xi, Yi, Di). If Di is rendered as a color or an intensity, the resulting eye diagram includes a representation (the Di) of a normalized density of transitions at each point (Xi, Yi), relative to that group as a whole.

Abstract: The time needed to perform an eye diagram measurement is minimized by initially randomly investigating the (X, Y)i that lie on a “starting” line crossing the sample space and expected to intersect any eye diagram. This finds a location on the eye diagram. Then the eye diagram is traversed as it is discovered by investigating nearest neighbors of locations found to belong to the eye diagram. Two arrays E and L of bits are established. The bits of E represent “eligible” (X, Y)i, while those of L represent “likely” (X, Y)i. At the very start of the measurement all bits in the eligible array E are set and all those in the likely array L are cleared, except that the starting line is established by setting in L and clearing in E locations for the corresponding (X, Y)i. Thereafter, locations in L that have 1s are measured in a randomly selected order.

Abstract: A system that allows an end user to optimize the performance of a logic analyzer quickly and easily is disclosed. A visual display allowing a user to see a data valid window and relative sample positions is provided. Direct graphical manipulation of the sample position allows for quick and accurate setting of sample positions. The present invention provides a graphical user interface generally comprised of the following components: a stable and transitioning data display; bus/signal labels; sample position time scale; an information icon; a timestamp icon; a graphical representation of suggested and selected sample position; a text display of selected sample position; and a legend. The present invention sets up the logic analyzer to correctly sample data from high speed, low margin systems. It measures data signals from the device under test relative to the user's state clock and automatically suggests the sampling position offset for each channel of the analyzer.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).

Abstract: The time needed to perform an eye diagram measurement is minimized by initially randomly investigating the (X, Y)i that lie on a “starting” line crossing the sample space and expected to intersect any eye diagram. This finds a location on the eye diagram. Then the eye diagram is traversed as it is discovered by investigating nearest neighbors of locations found to belong to the eye diagram. Two arrays E and L of bits are established. The bits of E represent “eligible” (X, Y)i, while those of L represent “likely” (X, Y)i. At the very start of the measurement all bits in the eligible array E are set and all those in the likely array L are cleared, except that the starting line is established by setting in L and clearing in E locations for the corresponding (X, Y)i. Thereafter, locations in L that have Is are measured in a randomly selected order.

Abstract: Delay induced apparent amplitude desensitization in a data signal channel and its accompanying worm-like distortion in an Eye Diagram Analyzer is avoided by altering the measurement to avoid the need for any substantial delay in the path of the data channel threshold comparison signals. In a first technique, only enough delay will be inserted in the data channels to produce the relative adjustments needed to compensate for skew between the data channels, as determined by a calibration operation, and it is these de-skewed, but otherwise un-delayed, data threshold comparison signals that are, in rapid succession, clocked into the latches whose difference registers a hit at a given (time, voltage) pair. The clock path delay is then varied from a minimal value to a sufficiently large value capable of spanning a desired the number of eye diagram cycles.

Abstract: Once an eye diagram measurement is begun and there is an eye diagram displayed, different on-screen measurement tools may be used singly, or in combination. Each measurement involves indicating with cursors and line segments regions of the eye diagram that are of interest, and a parameter or parameters associated with each measurement tool in use is reported in a (usually) separate area of the display. An Eye Limits measurement allows the specification of a point within an eye diagram, whereupon it finds and reports the eye diagram coordinates first encountered along horizontal and vertical lines extended from the selected point (i.e., “eye opening” size). The coordinates of the point itself are also reported. A Four Point Box measurement allows the construction on the eye diagram of a rectangle having sides parallel to the coordinate axes of the eye diagram.

Abstract: Once an eye diagram measurement is begun and there is an eye diagram displayed, different on-screen measurement tools may be used singly, or in combination. Each measurement involves indicating with cursors and line segments regions of the eye diagram that are of interest, and a parameter or parameters associated with each measurement tool in use is reported in a (usually) separate area of the display. An Eye Limits measurement allows the specification of a point within an eye diagram, whereupon it finds and reports the eye diagram coordinates first encountered along horizontal and vertical lines extended from the selected point (i.e., “eye opening” size). The coordinates of the point itself are also reported. A Four Point Box measurement allows the construction on the eye diagram of a rectangle having sides parallel to the coordinate axes of the eye diagram.

Abstract: An eye diagram analyzer can assign a plurality of SUT data signals to be members of a labeled group of channels. There may be a plurality of such groups. The measured data for components within a group can be merged according to various different modes into a composite eye diagram presentation. When a composite eye diagram is being displayed, the operator may position a screen pointer (cursor) over some interesting part of the eye diagram, and the analyzer will display a list those channels that contributed to the displayed pixels in that part of the eye diagram, as well as other related information. The operator may also select a channel from among the group, and then have the displayed pixels for which it is responsible be displayed in a selected color or otherwise highlighted in a way that allows them to be distinguished from all others.

Abstract: Delay induced apparent amplitude desensitization in a data signal channel and its accompanying worm-like distortion in an Eye Diagram Analyzer is avoided by altering the measurement to avoid the need for any substantial delay in the path of the data channel threshold comparison signals. In a first technique, only enough delay will be inserted in the data channels to produce the relative adjustments needed to compensate for skew between the data channels, as determined by a calibration operation, and it is these de-skewed, but otherwise un-delayed, data threshold comparison signals that are, in rapid succession, clocked into the latches whose difference registers a hit at a given (time, voltage) pair. The clock path delay is then varied from a minimal value to a sufficiently large value capable of spanning a desired the number of eye diagram cycles.

Abstract: An eye diagram analyzer can assign a plurality of SUT data signals to be members of a labeled group of channels merged into a composite eye diagram presentation. When a composite eye diagram is being displayed, the operator may select a channel from among the group, and then have the pixels associated with that channel be displayed in an altered manner (highlighted) that allows them to be distinguished from all others, to determine if the behavior of that channel contributes to a condition in the eye diagram that is of interest. The menu from which channels may be selected includes at least one button in a fixed location, and which when clicked on, automatically selects the next item in the list within that menu. In this way the mouse can be positioned just once, and then clicked as often as needed without further motion, allowing the operator to continuously observe, without re-direction of his visual attention, what effect, if any, is produced in the composite eye diagram.

Abstract: An eye diagram analyzer can assign a plurality of SUT data signals to be members of a labeled group of channels. There may be a plurality of such groups. The measured data for components within a group can be merged according to various different modes into a composite eye diagram presentation. When a composite eye diagram is being displayed, the operator may position a screen pointer (cursor) over some interesting part of the eye diagram, and the analyzer will display a list those channels that contributed to the displayed pixels in that part of the eye diagram, as well as other related information. The operator may also select a channel from among the group, and then have the displayed pixels for which it is responsible be displayed in a selected color or otherwise highlighted in a way that allows them to be distinguished from all others.

Abstract: A system is disclosed for enabling a user to specify a trigger condition of a signal or bus by enabling the user to graphically select the signal or bus from a hierarchically arranged list of signal or bus names. The user may make this selection from a graphical user interface of a signal measurement system. The user also graphically selects the signal trigger condition. A trigger-specification element identifying the trigger condition is visually associated with a displayed name of the first signal or bus. The user may select the signal trigger condition of the first signal or bus by selecting the first trigger-specification element. The signal measurement system may be a logic analyzer. The hierarchically arranged list may be vertically aligned and each signal or bus name may be visually associated with one of a first group of trigger-specification elements by horizontal alignment.

Abstract: An eye diagram analyzer assigns a plurality of SUT data signals to be members of a labeled group of channels. There may be a plurality of such groups. In addition to mere superposition in an (X, Y) display space of the various i-many (X, Y)-valued pixels for individual component eye diagrams associated with that group, other measured data for those pixels within a group can be merged in various different modes to produce corresponding composite eye diagram presentations. E.g., in a Normalized Signal Density Mode the number of hits at each trial measurement point is summed over all channels in the group, and then divided by the total number of clock cycles measured for the ith measurement point in that group to produce a density Di associated with the corresponding ith pixel: (Xi, Yi, Di). If Di is rendered as a color or an intensity, the resulting eye diagram includes a representation (the Di) of a normalized density of transitions at each point (Xi, Yi), relative to that group as a whole.

Abstract: A system and method are provided to evaluate logical values from target systems. The system includes a configuration in a field programmable gate array for performing a doubly bounded comparison. The configuration advantageously allows the user to determine when values are greater than or less than a predefined value while employing a reduced number of lookup tables in the field programmable gate array. The configuration includes an input to receive a parallel logical value. The system also includes a number of equality lookup tables configured to detect an equality between a portion of the logical value and a portion of a predefined value. The system also includes a number of inequality lookup tables configured to determine a type of an inequality between the portion of the logical value and the portion of the predefined value. The predefined value is preprogrammed and downloaded to the equality lookup tables at startup.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).