Patents by Inventor Richard Alfred Beaupre
Richard Alfred Beaupre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120146234Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Inventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
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Publication number: 20120009733Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Inventors: Eladio Clemente Delgado, Richard Alfred Beaupre, Stephen Daley Arthur, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan Mcconnelee, Raymond Albert Fillion
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Patent number: 8076696Abstract: A device is provided that includes a first conductive substrate and a second conductive substrate. A first power semiconductor component having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal can also be electrically coupled to the first conductive substrate, while a negative terminal can be electrically coupled to the second power semiconductor component, and an output terminal may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.Type: GrantFiled: October 30, 2009Date of Patent: December 13, 2011Assignee: General Electric CompanyInventors: Richard Alfred Beaupre, Eladio Clemente Delgado, Ljubisa Dragoljub Stevanovic
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Publication number: 20110300725Abstract: A dual pole busbar power connector including opposing elements configured to form a slot configured to receive a dual-pole blade therebetween. The slot extends from busbars to opposing element distal ends. The opposing elements each includes: a first contact extending into the slot from the opposing element; and a second contact extending into the slot from the opposing element and disposed farther from a slot busbar end than the first contact. When the dual-pole blade is inserted in the slot the first contact contacts a respective blade element at a location in the slot more proximate the slot busbar end than a slot distal end.Type: ApplicationFiled: June 3, 2010Publication date: December 8, 2011Inventors: Eladio Clemente Delgado, Ljubisa Stevanovic, Richard Alfred Beaupre
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Patent number: 8049338Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.Type: GrantFiled: April 7, 2006Date of Patent: November 1, 2011Assignee: General Electric CompanyInventors: Eladio Clemente Delgado, Richard Alfred Beaupre, Stephen Daley Arthur, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion
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Publication number: 20110139495Abstract: A circuit board includes a solder wettable surface and a metal mask configured to restrict solder from flowing outside the solder wettable surface of the circuit board.Type: ApplicationFiled: February 25, 2011Publication date: June 16, 2011Applicant: GENERAL ELECTRIC COMPANYInventors: Arun Virupaksha Gowda, Kevin Matthew Durocher, James Wilson Rose, Paul Jeffrey Gillespie, Richard Alfred Beaupre, David Richard Esler
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Publication number: 20110101515Abstract: A device is provided that includes a first conductive substrate and a second conductive substrate. A first power semiconductor component having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal can also be electrically coupled to the first conductive substrate, while a negative terminal can be electrically coupled to the second power semiconductor component, and an output terminal may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Applicant: GENERAL ELECTRIC COMPANYInventors: Richard Alfred Beaupre, Eladio Clemente Delgado, Ljubisa Dragoljub Stevanovic
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Patent number: 7919714Abstract: An assembly including a solder wettable surface is provided. The assembly also includes a metal mask configured to restrict solder from flowing outside the solder wettable surface.Type: GrantFiled: May 9, 2007Date of Patent: April 5, 2011Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Kevin Matthew Durocher, James Wilson Rose, Paul Jeffrey Gillespie, Richard Alfred Beaupre, David Richard Esler
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Patent number: 7915944Abstract: One embodiment is a gate drive circuitry for switching a semiconductor device having a non-isolated input, the gate drive circuitry having a first circuitry configured to turn-on the semiconductor device by imposing a current on a gate of the semiconductor device so as to forward bias an inherent parasitic diode of the semiconductor device. There is a second circuitry configured to turn-off the semiconductor device by imposing a current on the gate of the semiconductor device so as to reverse bias the parasitic diode of the semiconductor device wherein the first circuitry and the second circuitry are coupled to the semiconductor device respectively through a first switch and a second switch.Type: GrantFiled: June 30, 2009Date of Patent: March 29, 2011Assignee: General Electric CompanyInventors: Antonio Caiafa, Jeffrey Joseph Nasadoski, John Stanley Glaser, Juan Antonio Sabate, Richard Alfred Beaupre
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Patent number: 7898807Abstract: A substrate for power electronics mounted thereon, comprises a middle ceramic layer having a lower surface and an upper surface, an upper metal layer attached to the upper surface of the middle ceramic layer, and a lower metal layer attached to the lower surface of the middle ceramic layer. The lower metal layer has a plurality of millichannels configured to deliver a coolant for cooling the power electronics, wherein the millichannels are formed on the lower metal layer prior to attachment to the lower surface of the middle ceramic layer. Methods for making a cooling device and an apparatus are also presented.Type: GrantFiled: March 9, 2009Date of Patent: March 1, 2011Assignee: General Electric CompanyInventors: Richard Alfred Beaupre, Ljubisa Dragoljub Stevanovic
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Publication number: 20100302734Abstract: A heatsink assembly for cooling a heated device includes a ceramic substrate having a plurality of cooling fluid channels integrated therein. The ceramic substrate includes a topside surface and a bottomside surface. A layer of electrically conducting material is bonded or brazed to only one of the topside and bottomside surfaces of the ceramic substrate. The electrically conducting material and the ceramic substrate have substantially identical coefficients of thermal expansion.Type: ApplicationFiled: May 29, 2009Publication date: December 2, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Richard Alfred Beaupre, Ljubisa Dragoljub Stevanovic, Dieter Gerhard Brunner
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Patent number: 7829386Abstract: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.Type: GrantFiled: August 28, 2007Date of Patent: November 9, 2010Assignee: General Electric CompanyInventors: Raymond Albert Fillion, Richard Alfred Beaupre, Ahmed Elasser, Robert John Wojnarowski, Charles Steven Korman
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Publication number: 20100277868Abstract: A power module includes one or more semiconductor power devices bonded to an insulated metal substrate (IMS). A plurality of cooling fluid channels is integrated into the IMS.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Richard Alfred Beaupre, Peter Almern Losee, Xiaochun Shen, John Stanley Glaser, Joseph Lucian Smolenski, Adam Gregory Pautsch
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Publication number: 20100271081Abstract: One embodiment is a gate drive circuitry for switching a semiconductor device having a non-isolated input, the gate drive circuitry having a first circuitry configured to turn-on the semiconductor device by imposing a current on a gate of the semiconductor device so as to forward bias an inherent parasitic diode of the semiconductor device. There is a second circuitry configured to turn-off the semiconductor device by imposing a current on the gate of the semiconductor device so as to reverse bias the parasitic diode of the semiconductor device wherein the first circuitry and the second circuitry are coupled to the semiconductor device respectively through a first switch and a second switch.Type: ApplicationFiled: June 30, 2009Publication date: October 28, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Antonio Caiafa, Jeffrey Joseph Nasadoski, John Stanley Glaser, Juan Antonio Sabate, Richard Alfred Beaupre
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Patent number: 7817422Abstract: A heat sink for directly cooling at least one electronic device package is provided. The electronic device package has an upper contact surface and a lower contact surface. The heat sink comprises a cooling piece formed of at least one thermally conductive material. The cooling piece defines multiple inlet manifolds configured to receive a coolant and multiple outlet manifolds configured to exhaust the coolant. The inlet and outlet manifolds are interleaved. The cooling piece further defines multiple millichannels configured to receive the coolant from the inlet manifolds and to deliver the coolant to the outlet manifolds. The millichannels and inlet and outlet manifolds are further configured to directly cool one of the upper and lower contact surface of the electronic device package by direct contact with the coolant, such that the heat sink comprises an integral heat sink.Type: GrantFiled: August 18, 2008Date of Patent: October 19, 2010Assignee: General Electric CompanyInventors: Satish Sivarama Gunturi, Mahadevan Balasubramaniam, Ramakrishna Venkata Mallina, Richard Alfred Beaupre, Le Yan, Richard S. Zhang, Ljubisa Dragoljub Stevanovic, Adam Gregory Pautsch, Stephen Adam Solovitz
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Publication number: 20100230800Abstract: A power module includes one or more semiconductor power devices having a power overlay (POL) bonded thereto. A first heat sink is bonded to the semiconductor power devices on a side opposite the POL. A second heat sink is bonded to the POL opposite the side of the POL bonded to the semiconductor power devices. The semiconductor power devices, POL, first channel heat sink, and second channel heat sink together form a double side cooled power overlay module. The second channel heat sink is bonded to the POL solely via a compliant thermal interface material without the need for planarizing, brazing or metallurgical bonding.Type: ApplicationFiled: March 13, 2009Publication date: September 16, 2010Inventors: Richard Alfred Beaupre, Arun Virupaksha Gowda, Ljubisa Dragol jub Stevanovic, Stephen Adam Solovitz
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Publication number: 20100226093Abstract: A substrate for power electronics mounted thereon, comprises a middle ceramic layer having a lower surface and an upper surface, an upper metal layer attached to the upper surface of the middle ceramic layer, and a lower metal layer attached to the lower surface of the middle ceramic layer. The lower metal layer has a plurality of millichannels configured to deliver a coolant for cooling the power electronics, wherein the millichannels are formed on the lower metal layer prior to attachment to the lower surface of the middle ceramic layer. Methods for making a cooling device and an apparatus are also presented.Type: ApplicationFiled: March 9, 2009Publication date: September 9, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Richard Alfred Beaupre, Ljubisa Dragoljub Stevanovic
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Publication number: 20100175857Abstract: A cooling device comprises an upper surface configured to contact the baseplate, an inlet manifold configured to receive a coolant, an outlet manifold configured to exhaust the coolant, and at least one set of millichannels in the upper surface. The at least one set of the millichannels defines at least one heat sink region with at least one groove about one or more millichannels in the respective heat sink region with the groove configured to receive a seal. The at least one heat sink region establishes direct contact of the coolant with the baseplate, and the millichannels are configured to receive the coolant from the inlet manifold and to deliver the coolant to the outlet manifold. An apparatus and a stack are also presented.Type: ApplicationFiled: January 15, 2009Publication date: July 15, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: William Dwight Gerstler, Joseph Lucian Smolenski, Richard Alfred Beaupre, Stephen Adam Solovitz
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Publication number: 20100157526Abstract: A cooling device includes a ceramic substrate with a metal layer bonded to an outer planar surface. The cooling device also includes a channel layer bonded to an opposite side of the ceramic substrate and a manifold layer bonded to an outer surface of the channel layer. The substrate layers are bonded together using a high temperature process such as brazing to form a single substrate assembly. A plenum housing is bonded to the single substrate assembly via a low temperature bonding process such as adhesive bonding and is configured to provide extended manifold layer inlet and outlet ports.Type: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Richard Alfred Beaupre, Ljubisa Dragoljub Stevanovic, Daniel Jason Erno, Charles Gerard Woychik
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Publication number: 20100038058Abstract: A heat sink for directly cooling at least one electronic device package is provided. The electronic device package has an upper contact surface and a lower contact surface. The heat sink comprises a cooling piece formed of at least one thermally conductive material. The cooling piece defines multiple inlet manifolds configured to receive a coolant and multiple outlet manifolds configured to exhaust the coolant. The inlet and outlet manifolds are interleaved. The cooling piece further defines multiple millichannels configured to receive the coolant from the inlet manifolds and to deliver the coolant to the outlet manifolds. The millichannels and inlet and outlet manifolds are further configured to directly cool one of the upper and lower contact surface of the electronic device package by direct contact with the coolant, such that the heat sink comprises an integral heat sink.Type: ApplicationFiled: August 18, 2008Publication date: February 18, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Satish Sivarama Gunturi, Mahadevan Balasubramaniam, Ramakrishna Venkata Mallina, Richard Alfred Beaupre, Le Yan, Richard S. Zhang, Ljubisa Dragoljub Stevanovic, Adam Gregory Pautsch, Stephen Adam Solovitz