Abstract: A heat sink for cooling at least one electronic device package is provided. The electronic device package has an upper contact surface and a lower contact surface. The heat sink comprises at least one thermally conductive material and defines multiple inlet manifolds configured to receive a coolant, multiple outlet manifolds configured to exhaust the coolant, and multiple millichannels configured to receive the coolant from the inlet manifolds and to deliver the coolant to the outlet manifolds. The manifolds and millichannels are disposed proximate to the respective one of the upper and lower contact surface of the electronic device package for cooling the respective surface with the coolant.

Abstract: A structural building component for a residential or light commercial building includes a PV laminate and a plastic frame disposed at least around the PV laminate. The plastic frame includes a first electrical connector for communication with the PV laminate and receptive to electrical connection with a contiguous PV laminate. The first electrical connector is configured to facilitate electrical and mechanical connection with the contiguous PV laminate and the frame includes a means for facilitating attachment to the building structure.

Abstract: A power circuit package includes a base including a substrate, a plurality of interconnect circuit layers over the substrate with each including a substrate insulating layer patterned with substrate electrical interconnects, and via connections extending from a top surface of the substrate to at least one of the substrate electrical interconnects; and a power semiconductor module including power semiconductor devices each including device pads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure including a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections.

Abstract: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

Abstract: An assembly including a solder wettable surface is provided. The assembly also includes a metal mask configured to restrict solder from flowing outside the solder wettable surface.

Abstract: A current sensing system for estimating current in substantially parallel planar conductors. The system includes a magnetostrictive optical sensor including an optical sensing element coupled to a magnetostrictive element and disposed between substantially parallel planar conductors, wherein the magnetostrictive element is configured to cause a strain in the optical sensing element in the presence of a magnetic field between the substantially parallel planar conductors, and wherein the optical sensing element is configured to receive an optical interrogation signal and provide a wavelength modulated data signal indicative of magnitude of the current flowing through the conductors.

Abstract: A power module includes a substrate that includes an upper layer, an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern and is configured for receiving power devices. The electrical insulator is disposed between the upper layer and the thermal coupling layer. The thermal coupling layer is configured for thermal coupling to a heat sink. The power module further includes at least one laminar interconnect that includes first and second electrically conductive layers and an insulating layer disposed between the first and second electrically conductive layers. The first electrically conductive layer of the laminar interconnect is electrically connected to the upper layer of the substrate. Electrical connections connect a top side of the power devices to the second electrically conductive layer of the laminar interconnect.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.