Patents by Inventor Richard C. Murphy
Richard C. Murphy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11650941Abstract: Systems, apparatuses, and methods related to a computing tile are described. The computing tile may perform operations on received data to extract some of the received data. The computing tile may perform operations without intervening commands. The computing tile may perform operations on data streamed through the computing tile to extract relevant data from data received by the computing tile. In an example, the computing tile is configured to receive a command to initiate an operation to reduce a size of a block of data from a first size to a second size. The computing tile can then receive a block of data from a memory device coupled to the apparatus. The computing tile can then perform an operation on the block of data to extract predetermined data from the block of data to reduce a size of the block of data from a first size to a second size.Type: GrantFiled: October 6, 2021Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Vijay Ramesh, Allan Porterfield, Anton Korzh
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Patent number: 11636323Abstract: Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.Type: GrantFiled: June 29, 2020Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Richard C. Murphy
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Publication number: 20230111878Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator to increase the efficiency of the host and/or accelerator.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
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Publication number: 20230103659Abstract: Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template.Type: ApplicationFiled: December 1, 2022Publication date: April 6, 2023Inventors: Honglin Sun, Glen E. Hush, Richard C. Murphy
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Publication number: 20230100557Abstract: Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.Type: ApplicationFiled: November 21, 2022Publication date: March 30, 2023Inventors: Reshmi Basu, Richard C. Murphy
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Patent number: 11614894Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.Type: GrantFiled: May 4, 2021Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
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Patent number: 11609852Abstract: Systems, apparatuses, and methods related to hierarchical memory are described. A hierarchical memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. Logic circuitry can be configured to determine that a request to access a persistent memory device corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device. Access data and control messages can be transferred between or within a memory device, including to or from a multiplexer and/or a state machine. A state machine can include logic circuitry configured to transfer interrupt request messages to and receive interrupt request messages.Type: GrantFiled: May 4, 2021Date of Patent: March 21, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Anton Korzh, Richard C. Murphy
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Patent number: 11599475Abstract: An example includes a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.Type: GrantFiled: April 5, 2021Date of Patent: March 7, 2023Assignee: Micron Technology, Inc.Inventor: Richard C. Murphy
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Patent number: 11594274Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.Type: GrantFiled: January 25, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventor: Richard C. Murphy
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Patent number: 11593002Abstract: Systems, apparatuses, and methods related to multiple artificial neural networks (ANNs) in memory. Such ANNs can be implemented within a memory system (including a number of memory devices) at different granularities. For example, multiple ANNs can be implemented within a single memory device and/or a single ANN can be implemented over multiple memory devices (such that multiple memory devices are configured as a single ANN). The memory system having multiple ANNs can operate each ANN independently from each other such that multiple ANN operations can be concurrently performed.Type: GrantFiled: May 11, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Patent number: 11586556Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving a request to access data via an input/output (I/O) device, determining whether the data is stored in a non-persistent memory device or a persistent memory device, and redirecting the request to access the data to logic circuitry in response to determining that the data is stored in the persistent memory device.Type: GrantFiled: September 29, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
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Patent number: 11579882Abstract: Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.Type: GrantFiled: March 25, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
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Publication number: 20230043636Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.Type: ApplicationFiled: October 21, 2022Publication date: February 9, 2023Inventors: Jason T. Zawodny, Kelley D. Dobelstein, Timothy P. Finkbeiner, Richard C. Murphy
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Publication number: 20230020912Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.Type: ApplicationFiled: September 16, 2022Publication date: January 19, 2023Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11556759Abstract: Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template.Type: GrantFiled: August 6, 2019Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Honglin Sun, Glen E. Hush, Richard C. Murphy
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Patent number: 11537464Abstract: Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.Type: GrantFiled: June 14, 2019Date of Patent: December 27, 2022Assignee: Micron Technology, Inc.Inventors: Reshmi Basu, Richard C. Murphy
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Patent number: 11526289Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator.Type: GrantFiled: July 1, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
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Publication number: 20220392499Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Publication number: 20220357851Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Reshmi Basu, Richard C. Murphy
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Patent number: 11494078Abstract: Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (TLB).Type: GrantFiled: December 11, 2020Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventors: John D. Leidel, Richard C. Murphy