Abstract: A hydrostatic positive displacement machine has a cylinder drum (4) located in a housing (9) and rotatable around an axis of rotation (2). During rotation of the cylinder drum (4), a piston bore (5) is placed in alternating communication with an inlet side (E) and an outlet side (A). The inlet side (E) and outlet side (A) comprise connections (21; 22) to a control plate (12). A reversing device (30) is located in a reversing area (25; 26) between the connections (21, 22) on the control plate (12). The reversing device (30) damps the pressure adjustment between a displacement chamber (V) and the pressure present in the connection (21; 22). The reversing device (30) includes at least two flow connections which are actuated simultaneously by the displacement chamber (V) as it moves along the reversing area (25; 26).

Abstract: A hydrostatic positive displacement machine has a cylinder drum (4) located in a housing (9) and rotatable around an axis of rotation (2). During rotation of the cylinder drum (4), a piston bore (5) is placed in alternating communication with an inlet side (E) and an outlet side (A). The inlet side (E) and outlet side (A) comprise connections (21; 22) to a control plate (12). A reversing device (30) is located in a reversing area (25; 26) between the connections (21, 22) on the control plate (12). The reversing device (30) damps the pressure adjustment between a displacement chamber (V) and the pressure present in the connection (21; 22). The reversing device (30) includes at least two flow connections which are actuated simultaneously by the displacement chamber (V) as it moves along the reversing area (25; 26).

Abstract: A control valve device (1) for the control of a dual-action consumer (2) has a control valve (3) that controls the connection of a pressure fluid line (6a) that forms the admission side of the consumer (2) with a pump and an additional pressure fluid line (6b) that forms the return side of the consumer (2) with a reservoir. A regeneration function allows the return side of the consumer (2) to be connected with the admission side of the consumer (2). The regeneration function has a short circuit device (10) located between the consumer (2) and the control valve (3). For the regeneration function, the connection of the additional pressure fluid line (6b) that forms the return side of the consumer (2) with the reservoir can be blocked by a shutoff valve device (20) located between the consumer (2) and the control valve (3).

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.

Abstract: A control valve device (1) for the control of a dual-action consumer (2) has a control valve (3) that controls the connection of a pressure fluid line (6a) that forms the admission side of the consumer (2) with a pump and an additional pressure fluid line (6b) that forms the return side of the consumer (2) with a reservoir. A regeneration function allows the return side of the consumer (2) to be connected with the admission side of the consumer (2). The regeneration function has a short circuit device (10) located between the consumer (2) and the control valve (3). For the regeneration function, the connection of the additional pressure fluid line (6b) that forms the return side of the consumer (2) with the reservoir can be blocked by a shutoff valve device (20) located between the consumer (2) and the control valve (3).

Abstract: A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.

Abstract: A bus arbitration algorithm precisely controls the relative bus channel bandwidth allocated to each master device by considering the direction of, and/or the bus channel bandwidth consumed by, a bus transaction. At least one weighting register is associated with each master device; in one embodiment, one weighting register per bus channel. The register is periodically loaded with a proportionate share of the available bus bandwidth. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. In the case of equal initial allocation of relative bandwidth share, master devices that consume bus channel bandwidth will have relatively low priority; master devices that do not consume bus channel bandwidth retain relatively high priority.

Abstract: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

Abstract: A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with transmit and receive channels. The transmit channel may have a plurality of sub-channels. The sending component may be configured to broadcast on each of the sub-channels information comprising read and write address locations, read and write control signals, and write data on each of the sub-channels. The receiving component may be configured to store the write data and retrieve read data in response to the information broadcast on any of the sub-channels, and broadcast the retrieved read data on the receive channel to the sending component. The sending component may further be configured to provide to the receiving component independent signaling for each of the sub-channels, the independent signaling being sufficient to allow the receiving component to determine the type of information broadcast on each of the sub-channels.

Abstract: A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to each of the processors in a second tier. The bus arbiter may sequentially grant bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights, and grant bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight. When multiple processors are requesting access to the bus, the bus arbiter may grant bus access to the requesting processor with the highest weight in the highest tier.

Abstract: A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending component configured to broadcast a payload to the receiving component over the transmit channel, interrupt the broadcast of the payload to signal a new bus operation to the receiving component over the transmit channel, and resume the broadcast of the payload over the transmit channel. The processing system may include an algorithm that prevents small payloads from being interrupted to initiate a new bus operation. The algorithm may also be used to limit the number of times a single write operation may be interrupted to initiate a new bus operation.

Abstract: A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus; a memory region coupled to the bus; and a plurality of processing components having access to the memory region over the bus, each of the processing components being configured to perform a semaphore operation to gain access to the memory region by simultaneously requesting a read operation and a write operation to a semaphore location over the bus.

Abstract: A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.

Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.

Abstract: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.