Abstract: A method and system for forwarding interrupt requests from a source device to a destination device. A controller bridge receives data, from a source device, for a destination device and stores the incoming data in a data queue. An interrupt request is received from the source device for the destination device and forwarded to the destination device in response to completing a transfer of the data from the source device to the destination device. If data received from the source device for the destination device are pending in the data queue, the interrupt request is rejected and the source may resubmit the interrupt request at a later time. If additional data are received from the source device for the destination device, the data may be rejected in response to an interrupt pending in the interrupt queue from the source device for the destination device.

Abstract: A processing system is disclosed with a sending component and a receiving component connected by a multiple address two channel bus. The sending device may broadcast on the first channel of the bus read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data. The sending component may also broadcast the read and write address information multiple address locations at a time. The receiving component may store the write data broadcast on the first channel based on the write address information, retrieve the read data from the receiving component based on the read address information, and broadcasting the retrieved read data on the second channel of the bus.

Abstract: A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

Abstract: A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.

Abstract: This invention relates to a device to reduce pulsations on a hydrostatic positive displacement units, such as an axial or radial piston machine working both as a pump and as a motor with a reversible direction of rotation. In the displacement units, at least one piston is mounted so that it can move longitudinally in a cylinder bore which forms a cylinder chamber. The device has a buffer element which is in communication with the high-pressure side and can be brought into connection with the cylinder chamber. The device reduces pulsations on hydrostatic positive displacement units by which the reversing actions of the cylinder chambers are optimized and the pulsations are effectively minimized in a broad bandwidth of operating conditions. A switchable valve, in particular a non-return valve which opens toward the cylinder chamber is located in a connecting channel between the buffer element and the cylinder chamber.

Abstract: A container for a compact product including a housing, a stem, and a follower engaged with the stem adapted to move axially within the container in response to rotation of the stem. The follower including a central tube threadingly engaged with the stem that is adapted to flex when the follower is in a retracted position and the stem is rotated, to permit the stem to rotate relative to the follower. A fingerwheel may be included to facilitate rotation of the stem.