Abstract: A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed.

Abstract: A data processing system includes exception handling circuitry to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank. Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.

Abstract: An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory.

Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated.

Abstract: An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing. The instruction decoding circuitry is responsive to a speculation barrier instruction to control the processing circuitry to prevent a subsequent operation, appearing in program order after the speculation barrier instruction, that has an address dependency on an earlier instruction preceding the speculation barrier instruction in the program order, from speculatively influencing allocations of entries in a cache. This provides protection against speculative cache-timing side-channel attacks.

Abstract: A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state.

Abstract: An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory.

Abstract: An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processors is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processor is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processor is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times.

Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.

Abstract: A data processing apparatus has processing circuitry which has a secure domain and a less secure domain of operation. When operating in the secure domain the processing circuitry has access to data that is not accessible in the less secure domain. In response to a control flow altering instruction, processing switches to a program instruction at a target address. Domain selection is performed to determine a selected domain in which the processing circuitry is to operate for the instruction at the target address. Domain checking can be performed to check which domains are allowed to be the selected domain determining the domain selection. A domain check error is triggered if the selected domain in the domain selection is not an allowed selected domain.

Abstract: An apparatus and method are provided for controlling use of bounded pointers. The apparatus includes storage to store bounded pointers, where each bounded pointer comprises a pointer value and associated attributes, with the associated attributes including range information indicative of an allowable range of addresses when using the pointer value. Processing circuitry is used to perform a signing operation on an input bounded pointer in order to generate an output bounded pointer in which a signature generated by the signing operation is contained within the output bounded pointer in place of specified bits of the input bounded pointer. In addition, the associated attributes include signing information which is set by the processing circuitry within the output bounded pointer to identify that the output bounded pointer has been signed. Such an approach provides increase resilience to control flow integrity attack when using bounded pointers.

Abstract: A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level.

Abstract: A data processing system (2) includes an instruction decoder (10) which decodes protected memory access instructions (LDR/STR) and less-protected memory access instructions (LDNPR/STNPR) to generate control signals for controlling a load store unit (12). The less-protected memory access instructions are associated with less restrictive memory access conditions than the protected memory access instructions. As an example, less-protected memory access instructions may be used to access shared memory regions (26, 28) whereas protected memory access instructions may not be used to access such shared regions. Conversely, less-protected memory access instructions may not be used to access private memory regions (30, 32, 34).

Abstract: An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry 50 to be implemented with reduced hardware and energy cost.

Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

Abstract: A data processing system (2) includes exception handling circuitry (26) to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank (20). Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register (32) characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.

Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.

Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.