Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).

Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.

Abstract: A data processing system comprising: ownership circuitry to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified from among a plurality of processes and independently of privilege level, said given owning process having exclusive rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of: private to said given owning process; and shared between said given owning process and at least one further source of memory access requests.

Abstract: A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

Abstract: A data processing apparatus (20) comprises processing circuitry (24, 25, 28) to execute a plurality of processes. An ownership table (50) comprises one or more entries (52) each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses.

Abstract: A processing apparatus has a memory protection unit (MPU) 38 and an address translation unit (ATU) 120 which operate concurrently for memory access operations performed by processing circuitry 22. The MPU 38 stores access permission data for corresponding regions of an address space. The ATU 120 stores address translation entries for defining virtual-to-physical mappings for corresponding pages of the address space. In response to a memory access operation specifying a target address, one of the MPU 38 and the ATU 120 is selected to handle the memory access operation based on the target address. If the MPU 38 is selected then the target address is a physical address and the MPU 38 checks access permissions using a corresponding set of permission data. If the ATU 120 is selected then the target address is a virtual address and is translated into a physical address using a corresponding translation entry.

Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated.

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

Abstract: A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

Abstract: A data processing system 2 includes a stack pointer register 26, 28, 30, 32 storing a stack pointer value for use in stack access operations to a stack data store 44, 46, 48, 50. Stack alignment checking circuitry 36 which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry 36 is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry 38 may be provided and independently selectively disabled in respect of any memory access.

Abstract: A data processing apparatus, method and computer program that perform an operation on one data element such as a register and conditionally select either that register or a further register on which no operation has been performed. The apparatus includes an instruction decoder configured to decode at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. Data processing operations are controlled by the instruction decoder and the data processor is responsive to the decoded at least one conditional select instruction where the condition does not have the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

Abstract: A processor is provided with a first memory protection unit applying a first set of permissions and a second memory protection unit applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied. The processor also includes a memory management unit which serves to translate from virtual addresses VA to physical addresses PA. A selectable one of the first memory protection unit and the memory management unit is active at any given time under control of a selection bit set by a hypervisor program executing at an exception level with higher privilege than the exception level at which the guest operating systems execute.

Abstract: Processing circuitry has a plurality of exception states for handling exception events, the exception states including a base level exception state and at least one further level exception state. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store. When the processing circuitry is in the base level exception state, stack pointer selection circuitry selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry. When the processing circuitry is a further exception state, the stack pointer selection circuitry selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.

Abstract: An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.

Abstract: A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element. Bitwise logical instructions are also described.

Abstract: A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

Abstract: A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level.