Abstract: A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.

Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.

Abstract: A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.

Abstract: A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

Abstract: A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.

Abstract: A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

Abstract: What is disclosed is a system for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single DUT on the set of tester I/O lines, and circuitry coupled to the set of tester I/O lines to receive the data values from the tester and to provide error values to the tester, the circuitry forwards the data values to each of the plurality of DUTs, the circuitry performs a first comparison of the values of two locations having corresponding addresses in different DUTs after reading from the locations, and in response generates the error values indicative of the first comparison. The circuitry may further perform a second comparison of the values of two different locations in the same DUT to generate further error values indicative of the second comparison.

Abstract: A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select memory bit cells in a particular I/O. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, VDD. The I/O is cleared by placing a predetermined logic state (typically 0) on the bitline nodes of the I/O and selectively coupling the local wordlines to the VDD node.

Abstract: A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiments a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.

Abstract: A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier.

Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.

Abstract: A hierarchical sense amp and write driver (SA/WD) circuitry architecture for compilable high-density memory. A predetermined number of secondary, or regional, SA/WD blocks segment the main array associated with the memory instance in multiple banks. Each secondary SA/WD block is coupled to a tertiary, or global, SA/WD block via a global I/O line operating to effectuate data I/O on a per I/O basis with respect to the memory instance. A select number of primary SA/WD blocks per each secondary SA/WD block are specified, wherein the primary SA/WD blocks segment a memory bank associated with a particular secondary SA/WD block into a plurality of sub-banks. Each primary SA/WD block is coupled to a select secondary SA/WD block associated therewith via a common regional I/O line. A select number of memory cells per bitline segment for each of the memory sub-banks may be specified as part of compiling a memory instance for a particular application.

Abstract: Self-timed clock circuitry for use in a compilable memory instance using a common timing synchronization node. A plurality of memory banks are provided in the memory instance wherein each memory bank is independently selectable by a bank select (BS) signal generated by a global control circuit. A global timing circuit is provided to drive a common node signal on the common timing synchronization node to a high value upon application of an external master clock and a memory enable signal to the memory instance. The global timing circuit is operable to drive the common node signal high for a predetermined time period. A local driver circuit associated with a particular memory bank selected by a specific BS signal takes over control of driving the common node signal thereafter so as to maintain its high state. Upon completing the memory access operation, a reference signal within the particular memory bank is driven low.

Abstract: A full signal swing differential output path circuit for rapidly transferring a latched data value on a pair of complementary global data nodes (QT and QB) to a single-ended output of a compilable memory instance. At least one tri-statable sense amplifier is disposed between the complementary global data nodes which operates to sense a small differential voltage between a pair of complementary bitlines disposed in a bank of memory storage cells during an access operation associated therewith. A pair of precharge pull up devices are provided for precharging the complementary global data nodes QT and QB to a predetermined voltage, e.g., VDD. In a preferred embodiment, the precharge pull up devices preferably comprise P-channel MOS (PMOS) devices and are actuatable by an active low precharge signal. A first output of the sense amp is coupled to one of the complementary global data nodes (QB) and the complementary output (i.e.

Abstract: The present invention includes a variable delay element that can be programmed by a combination of control signals whose values may be determined by a matrix of programming elements, preferably fuses. In a TEST mode, a multiplexer array decouples the matrix, and instead couples a combination of user provided TEST mode control signals to the variable delay element. TEST mode permits selection of a suitable delay by observing the effect on IC functionality of all available values of delay provided by these TEST mode user-provided control signals. Once a suitable delay has been determined, the matrix may be programmably altered to permanently store and provide to the variable delay element the appropriate pattern of control signals to produce such delay.

Abstract: MOS integrated circuit fabrication processes may be optimized for yield rather than for hot carrier lifetime by compensating for oversize MOS channel lengths with increased V.sub.cc power supply voltage, and by compensating for undersized MOS device channel lengths with decreased V.sub.cc. Where channel lengths are greater than necessary, V.sub.cc is increased to increase switching times, while still operating the integrated circuit in a regime ensuring at least a minimum hot carrier lifetime. A test MOS device is fabricated on the integrated circuit substrate and in a test mode the test device substrate current I.sub.bb is measured. The measured I.sub.bb is then correlated with known I.sub.bb data to ascertain whether the channel length and DC hot carrier lifetime are acceptable, both for the test device and all MOS devices in the integrated circuit. The measured I.sub.bb value may be used with a look-up table to manually adjust the V.sub.

Abstract: An input protection circuit protects MOS semiconductor circuits from electrostatic discharge voltages and from developing circuit latchup. The input protection circuit includes a low resistance input resistor, and two complementary true gated diodes. One true gated diode has a P-doped node coupled to the input node, and a gate and N-doped node coupled to a high voltage power supply node. The other true gated diode has a N-doped node coupled to the input node, and a gate and P-doped node coupled to a second power supply node.

Abstract: A static memory device is disclosed having an array of static memory cells, each memory cell having first and second cross-coupled inverters. All of the memory cells have distinct power voltage connections to the first and second inverters of each memory cell. When a reset signal occurs, the device's reset apparatus generates a voltage imbalance on the power voltage connections so that distinct voltage levels are applied to the first and second cross-coupled inverters of each memory cell. The voltage imbalance causes all of the memory cells in the array to be set into a predetermined state. In a preferred embodiment, the power voltage connections include a common high voltage power connection to all of the memory cells and distinct low voltage power connections to the first and second inverters of each memory cell.

Abstract: A static random access memory has a multiplicity of separate memory blocks, only one of which is activated during each memory access cycle. Each memory block has its own separate bit line equalization circuity which equalizes the voltages of each complementary bit line pair in the memory block. A write equalization decoder automatically, at the end of each write cycle, generates a decoded write recovery equalization pulse, which activates the bit line equalization circuitry only in the memory block to which data has been written. As a result, the process of equalizing the bit lines is removed from the critical timing path for accessing the memory after a write cycle, eliminating one of the primary problems associated with the use of address transition detection in static memory devices. In addition, the write recovery equalization pulse can be generated at high speed because the decoded write recovery equalization pulse drives only one of the multiplicity of separate memory blocks.