Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

Abstract: A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.

Abstract: A system and method for fabricating metal patterns are described. Multiple mandrels are formed on a first polysilicon layer which is on top of a first oxide layer. Each mandrel uses a second polysilicon on top of a first nitride. A spacer oxide and a spacer nitride are formed on the sidewalls of the mandrels to create double spacers. A second oxide layer is deposited followed by removing layers until the first nitride in the mandrels is reached. Areas are etched based on a selected method of multiple available methods until the first oxide layer is etched providing trenches for the metal patterns. Remaining materials on the first oxide layer are removed followed by metal being deposited in the trenches in the first oxide layer.

Abstract: A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.

Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell uses unidirectional tracks for each of the multiple power vertical metal 3 layer tracks and power horizontal metal 2 tracks. One or more of the multiple vertical metal 3 layer posts are routed with a minimum length based on a pitch of power horizontal metal 2 layer straps. One or more vertical metal 1 posts used for a power connection or a ground connection are routed from a top to a bottom of an active region permitting multiple locations to be used for connections to one of the multiple power horizontal metal 2 layer straps. Two or more power horizontal metal 2 layer straps are placed within a power metal 2 layer track without being connected to one another.

Abstract: A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.

Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer on top of an oxide layer which is on top of a metal layer. The process etches trenches into areas of the polysilicon layer where the repeated trenches determine a frequency of an oscillating wave structure to be formed later. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the polysilicon layer both on areas with the trenches and on areas without the trenches. A series of a barrier metal and a second polysilicon layer is deposited on the oscillating structure. The process completes the MIM capacitor with metal nodes contacting each of the top metal and the bottom metal of the oscillating structure.

Abstract: A system and method for fabricating non-planar devices while managing semiconductor processing yield and cost are described. A semiconductor device fabrication process forms a stack of alternating semiconductor layers. A trench is etched and filled with at least an oxide layer with a length at least that of a device channel length while being bounded by sites for a source region and a drain region. The process places a second silicon substrate on top of both the oxide layer in the trench and the top-most semiconducting layer of the stack. The two surfaces making contact by wafer bonding use the same type of semiconducting layer. The device is flipped such that the first substrate and the stack are on top of the second substrate. The process forms nanowires of a gate region from the stack in the top first substrate.

Abstract: A system and method for fabricating non-planar devices while managing semiconductor processing yield and cost are described. A semiconductor device fabrication process forms a stack of alternating semiconductor layers. A trench is etched and filled with at least an oxide layer with a length at least that of a device channel length while being bounded by sites for a source region and a drain region. The process places a second silicon substrate on top of both the oxide layer in the trench and the top-most semiconducting layer of the stack. The two surfaces making contact by wafer bonding use the same type of semiconducting layer. The device is flipped such that the first substrate and the stack are on top of the second substrate. The process forms nanowires of a gate region from the stack in the top first substrate.

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Abstract: A system and method for fabricating non-planar devices while managing short channel and heating effects are described. A semiconductor device fabrication process includes forming a non-planar device where the body of the device is insulated from the silicon substrate, but the source and drain regions are not insulated from the silicon substrate. The process builds a local silicon on insulator (SOI) while not insulating area around the source and drain regions from the silicon substrate. A trench is etched a length at least that of a channel length of the device while being bounded by a site for a source region and a site for a drain region. The trench is filled with relatively thick layers to form the local SOI. When nanowires of a gate are residing on top of the layer-filled trench, a second trench is etched into the top layer for depositing gate metal in the second trench.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Abstract: An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over one or more replacement metal gates on a semiconductor substrate. The mandrels include a first insulating material. Each mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. Mandrel spacers are formed around each insulating mandrel. The mandrel spacers include the first insulating material. Each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. A second insulating layer of the second insulating material is formed over the transistor. Trenches to the sources and drains of the gates are formed by removing the second insulating material from portions of the transistor between the mandrels. Trench contacts to the sources and drains of the gates are formed by depositing conductive material in the first trenches.

Abstract: A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.