Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.

Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.

Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.

Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.

Abstract: A method of forming metallization layers and vias as part of an interconnect structure within an integrated circuit ("IC") is disclosed. The metallization layers and vias are formed of an alloy consisting of tungsten and one or more other materials such as aluminum, gold, copper, cobalt, titanium, molybdenum or platinum. In the alternative, the alloy may include aluminum and exclude tungsten. The alloy that forms the metallization layers and vias is deposited onto the IC substrate using ionized cluster beam ("ICB") apparatus. The IC substrate is an "in-process" IC in that various active devices (e.g., bipolar and/or MOS transistors), resistors and capacitors are formed in the substrate using conventional techniques prior to the ICB deposition of the alloy layers. Intermediate IC substrate processing steps (e.g., patterning and etching to form the vias) may take place in-between ICB deposition steps.

Abstract: The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a patterned interlevel dielectric layer superjacent the substrate such that a segment of the substrate is exposed. Subsequently, a contact comprising a material having a grain size smaller than polycrystalline silicon is formed superjacent the patterned interlevel dielectric layer and the segment of the substrate exposed. The contact is then implanted with a dopant. Once implanted, the substrate is annealed to enable the dopant to diffuse from the contact into the base region impeded by the grain size to form an emitter region and thereby increase the Early voltage of the bipolar junction transistor.

Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor using a semiconductor substrate comprising a base, an emitter and a collector and an interface at the emitter, such that a carrier current conducts between the base and the emitter. Further, a first polysilicon layer is formed superjacent the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: The present invention teaches a method of making an isolation trench. First, a silicon on insulator ("SOI") structure is provided having a conductive layer superjacent the insulator of the SOI. Second, a trench is formed down to the insulator of the SOI, thereby creating a first and second conductive region. Third, a first silicon dioxide layer is formed conformally with the sidewalls of the first and second conductive region. Fourth, a second silicon dioxide layer is formed conformally and superjacent the first silicon dioxide layer. Fifth, the remaining areas unfilled in the trench are filled with an undoped polysilicon filling. Sixth, the polysilicon layer is planarized. Seventh, an oxide cap is formed on top of the polysilicon refill. Eight, an isolation mask is formed, and the active area openings within the structure are etched down to the single crystal silicon.

Abstract: The present invention teaches a low voltage coefficient MOS capacitor, and a method of making such a capacitor, having substantially uniform parasitic effects over an operating voltage range and a low voltage coefficient. The capacitor comprises a first conductive layer superjacent a silicon on insulator ("SOI") substrate. The first conductive layer comprises heavily doped silicon having a first conductivity type, while the substrate comprises a second conductivity type. Further, the capacitor comprises an isolation trench surrounding the first conductive layer filled with a dielectric material. Positioned superjacent the first conductive layer is a dielectric layer, thereby forming a dielectric shell on all sides of the first conductive layer except for its upper face. Moreover, a second conductive layer is positioned superjacent the dielectric layer to form a low voltage coefficient capacitor.

Abstract: A bipolar lateral device is disclosed having a high BV.sub.ceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region of the device and the resulting device has a BV.sub.ceo of 8 to 10 V. In another embodiment, the silicide is excluded from the surface of the polysilicon protecting the n-base width region and the polysilicon is maintained as intrinsic polysilicon. The resulting device has a BV.sub.ceo of about 20 V. The devices are useful as voltage clamping devices in programmable logic circuits which must withstand a collector to emitter reverse bias voltage that is sufficient to program either vertical fuse or lateral fuse devices.

Abstract: A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

Abstract: A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the substrate, and a silicon device layer disposed above the insulating layer. Vertical transistors may be formed in the device layer such that each transistor is fully dielectrically isolated from another and also from other similarly manufactured silicon devices in the silicon device layer.

Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wraparound silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Abstract: A bipolar lateral device is disclosed having a high BV.sub.ceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region of the device and the resulting device has a BV.sub.ceo of 8 to 10 V. In another embodiment, the silicide is excluded from the surface of the polysilicon protecting the n-base width region and the polysilicon is maintained as intrinsic polysilicon. The resulting device has a BV.sub.ceo of about 20 V. The devices are useful as voltage clamping devices in programmable logic circuits which must withstand a collector to emitter reverse bias voltage that is sufficient to program either vertical fuse or lateral fuse devices.

Abstract: A method for formation of silicide structures on a semiconductor device. Oxide sidewalls are formed upon and selectively removed from polysilicon contacts. Refractory metal is deposited and heated, unreacted metal is removed, leaving a metal silicide on selected polysilicon sidewalls.

Abstract: Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.