Abstract: There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an exposed portion of the strained silicon layer. The exposed portion of the strained silicon layer is amorphized and re-crystallized to a crystal structure having an orientation the same as the semiconductor substrate.

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract: The invention provides, in one aspect, a method of forming a semiconductor device including providing a semiconductor substrate that comprises a first portion having a crystal orientation and a second portion located over the first portion and having a different crystal orientation. An interfacial region is located between the first portion and second portion. A passivating dopant is implanted into the interfacial region to passivate unterminated bonds within the interfacial region.

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device.

Abstract: A method of forming a semiconductor device includes doping at least one region of an at least partially formed semiconductor device. The method further includes depositing at least one spacer layer outwardly from the at least one region of the at least partially formed semiconductor device. The at least one deposited spacer layer is formed in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the at least partially formed semiconductor device.

Abstract: A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).

Abstract: A semiconductor device includes a substrate and an oxide layer disposed outwardly from the substrate. The semiconductor device also includes a polysilicon layer disposed outwardly from the oxide layer, the oxide layer having an interface between the oxide layer and the polysilicon layer, the interface having asperities such that the barrier potential between the polysilicon layer and the substrate is reduced in response to the asperities.

Abstract: A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).

Abstract: A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device.

Abstract: Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.

Abstract: Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O2,O3, NO, N2O, H2O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: Gas purification resins are encapsulated in deformable, permeable polymer sheaths to form purification rings, gaskets or seals. A primary source of contaminants in advanced vacuum processors equipped with vacuum load-lock systems and process gas purifiers is from the leakage of outside ambient contaminants around O-ring seals. Using gas purification rings, gaskets or seals properly placed inside or outside of the outer O-ring seal, the level of contaminants (particularly hydrocarbons, oxygen and moisture) may be significantly reduced or eliminated. The gas purification ring is preferably a hydrocarbon and/or oxygen and/or moisture absorbing and/or adsorbing material encased within a contaminant permeable casing. The gas purification ring can be round or flattened and is preferably more resilient than the O-rings adjacent thereto which form the seal. An adhesive can be placed around the casing holding the purification resin to prevent movement from its purifying location.

Abstract: An integrated circuit comprises a dielectric layer disposed outwardly from a semiconductor substrate, the dielectric layer comprising at least one cavity having sidewalls extending from an outer surface of the dielectric layer inwardly toward the substrate. The integrated circuit further comprises a contaminant resistant barrier disposed outwardly from at least the sidewalls of the cavity in the dielectric layer.