Patents by Inventor Rikihiro Maruyama

Rikihiro Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230343682
    Abstract: A wire protecting part partially encloses a first lead frame and a second lead frame and has an enclosing surface from which the first and second lead frames protrude. The enclosing surface is parallel to semiconductor chips, and includes a water stop part protruding, from the enclosing surface, between the first and second lead frames.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 26, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Yoshinori ODA, Takahito HARADA
  • Patent number: 11721633
    Abstract: A circuit pattern, which is a second negative electrode wiring, and a horizontally extending area of a circuit pattern, which is a first negative electrode wiring, are connected electrically and mechanically by a vertically extending area of the circuit pattern and wires, which are an inter-negative-electrode wiring. As a result, N terminals and N1 terminals are equal in potential in a semiconductor device. The N terminals of a converter circuit section and the N1 terminals of an inverter circuit section are electrically connected to make the N terminals and the N1 terminals equal in potential.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 8, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaki Takahashi, Kousuke Komatsu, Rikihiro Maruyama
  • Patent number: 11626358
    Abstract: A semiconductor device, including a circuit pattern, a contact part and an external connection terminal. The contact part has a cylindrical through-hole and first and second opening ends opposite to each other, the second opening end being joined to the circuit pattern. The external connection terminal has a prismatic main body portion and first and second end portions, the second end portion being inserted into the through-hole from the first opening end of the contact part. The main body portion of the external connection terminal has an insertion prevented portion formed thereon. The contact part includes an insertion preventing portion formed on an inner circumferential surface of the through-hole, the insertion preventing portion being so positioned as to be substantially downstream, with respect to an insertion direction of the external connection terminal, from the main body portion of the external connection terminal inserted into the through-hole.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 11, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Seiichi Takahashi
  • Publication number: 20230014848
    Abstract: A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.
    Type: Application
    Filed: May 31, 2022
    Publication date: January 19, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Norihiro KOMIYAMA, Kunio KOBAYASHI, Yuto KOBAYASHI, Takahito HARADA, Hirohisa OYAMA, Masahiro SASAKI, Ryousuke USUI
  • Publication number: 20220208685
    Abstract: A circuit pattern, which is a second negative electrode wiring, and a horizontally extending area of a circuit pattern, which is a first negative electrode wiring, are connected electrically and mechanically by a vertically extending area of the circuit pattern and wires, which are an inter-negative-electrode wiring. As a result, N terminals and N1 terminals are equal in potential in a semiconductor device. The N terminals of a converter circuit section and the N1 terminals of an inverter circuit section are electrically connected to make the N terminals and the N1 terminals equal in potential.
    Type: Application
    Filed: October 29, 2021
    Publication date: June 30, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masaki TAKAHASHI, Kousuke KOMATSU, Rikihiro MARUYAMA
  • Patent number: 11337306
    Abstract: A semiconductor device including an insulated circuit board. The insulated circuit board includes an insulating board having an outer edge and a plurality of corners, and a plurality of circuit patterns formed on a front surface of the insulating board. The plurality of circuit patterns have a plurality of outer-edge corners facing the outer edge of the insulating board, among which outer-edge corners corresponding to the corners of the insulating board are smaller in curvature than outer-edge corners that do not correspond to the corners of the insulating board.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 17, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi Kai, Rikihiro Maruyama
  • Patent number: 11295997
    Abstract: A method of manufacturing a semiconductor device prepares contact members, each of which has a cylindrical through-hole, and column-shaped connection terminals, each having a polygonal shape in a cross-sectional view along a length direction thereof, wherein a length of a diagonal of the polygonal shape is greater than an inner diameter of the through-holes. Chamfers with a curvature for fitting an inner surface of the through-holes are formed at corners of the connection terminal, and the connection terminals are press-fitted into the through-holes of the contacts. By doing so, the area of contact where the connection terminals press-fitted into the contacts contact the inner circumferential surfaces of the through-holes of the contacts is increased. This increases the tensile load of the connection terminals fitted into the contacts.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: April 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Masaoki Miyakoshi
  • Publication number: 20210375734
    Abstract: A semiconductor device, including a circuit pattern, a contact part and an external connection terminal. The contact part has a cylindrical through-hole and first and second opening ends opposite to each other, the second opening end being joined to the circuit pattern. The external connection terminal has a prismatic main body portion and first and second end portions, the second end portion being inserted into the through-hole from the first opening end of the contact part. The main body portion of the external connection terminal has an insertion prevented portion formed thereon. The contact part includes an insertion preventing portion formed on an inner circumferential surface of the through-hole, the insertion preventing portion being so positioned as to be substantially downstream, with respect to an insertion direction of the external connection terminal, from the main body portion of the external connection terminal inserted into the through-hole.
    Type: Application
    Filed: March 26, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Seiichi TAKAHASHI
  • Patent number: 11164846
    Abstract: A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Kenshi Kai, Kazuya Adachi
  • Patent number: 11107784
    Abstract: A semiconductor device includes: a multilayer substrate which includes a circuit board and an insulating plate on which the circuit board is formed; and a contact part having a cylindrical hollow hole therein and an open end bonded to a bonding area on the front surface of the circuit board via bonding material. In the case of this semiconductor device, wettability of a contact area of the contact part with respect to the bonding material is approximately equal to wettability of at least the bonding area of the circuit board with respect to the bonding material. Thus, the rising of the bonding material into the hollow hole of the contact part during heating performed when the contact part is bonded to the circuit board is reduced.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 31, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Masaoki Miyakoshi, Masayuki Soutome, Kazuya Adachi, Takeshi Yokoyama
  • Publication number: 20210251075
    Abstract: A semiconductor device including an insulated circuit board. The insulated circuit board includes an insulating board having an outer edge and a plurality of corners, and a plurality of circuit patterns formed on a front surface of the insulating board. The plurality of circuit patterns have a plurality of outer-edge corners facing the outer edge of the insulating board, among which outer-edge corners corresponding to the corners of the insulating board are smaller in curvature than outer-edge corners that do not correspond to the corners of the insulating board.
    Type: Application
    Filed: December 28, 2020
    Publication date: August 12, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi KAI, Rikihiro MARUYAMA
  • Patent number: 11069643
    Abstract: A conductive plate has a front surface at a front side and a rear surface at a rear side. The front surface includes a first front surface on which a first arrangement region is disposed and a second front surface on which a second arrangement region is disposed. The first front surface has a height measured from the rear surface that is different from a height of the second front surface measured from the rear surface. Next, first and second bonding materials are respectively applied to the first and second arrangement regions. A first part is bonded to the first arrangement region via the first bonding material, and a second part is bonded to the second arrangement region via the second bonding material. The heights of the first and second arrangement regions set on the front surface on the conductive plate are different from each other.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 20, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi Kai, Rikihiro Maruyama
  • Patent number: 10978371
    Abstract: A semiconductor device including an insulated circuit board on which a semiconductor chip is mounted, and a housing implemented by a plurality of side-walls including at least a first pair of facing side-walls, each of the facing side-walls having joint edges configured to be jointed with the insulated circuit board, and each of the joint edges has an arc-shape such that a center in an extending direction of the joint edge protrudes toward the insulated circuit board more than both ends of the extending direction of the joint edge.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 13, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi Kai, Rikihiro Maruyama, Yoshihiro Miyazaki
  • Publication number: 20200328130
    Abstract: A case of a semiconductor device has sidewall portions which surround sides of a metal substrate along the sides and a coating portion which covers the front surface of the metal substrate surrounded by the sidewall portions and which has through ring holes corresponding to fixing holes. Protrusions are formed on inner surfaces of the sidewall portions opposed to one another in plan view with the ring holes therebetween. The metal substrate is inserted in this way into an area surrounded by the sidewall portions of the case and is reliably fixed. Furthermore, alignment is performed with accuracy between each fixing hole of the metal substrate inserted in this way and its corresponding ring hole of the case.
    Type: Application
    Filed: February 26, 2020
    Publication date: October 15, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Rikihiro MARUYAMA
  • Patent number: 10784176
    Abstract: A case of a semiconductor device has sidewall portions which surround sides of a metal substrate along the sides and a coating portion which covers the front surface of the metal substrate surrounded by the sidewall portions and which has through ring holes corresponding to fixing holes. Protrusions are formed on inner surfaces of the sidewall portions opposed to one another in plan view with the ring holes therebetween. The metal substrate is inserted in this way into an area surrounded by the sidewall portions of the case and is reliably fixed. Furthermore, alignment is performed with accuracy between each fixing hole of the metal substrate inserted in this way and its corresponding ring hole of the case.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 22, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Rikihiro Maruyama
  • Publication number: 20200286800
    Abstract: A method of manufacturing a semiconductor device prepares contact members, each of which has a cylindrical through-hole, and column-shaped connection terminals, each having a polygonal shape in a cross-sectional view along a length direction thereof, wherein a length of a diagonal of the polygonal shape is greater than an inner diameter of the through-holes. Chamfers with a curvature for fitting an inner surface of the through-holes are formed at corners of the connection terminal, and the connection terminals are press-fitted into the through-holes of the contacts. By doing so, the area of contact where the connection terminals press-fitted into the contacts contact the inner circumferential surfaces of the through-holes of the contacts is increased. This increases the tensile load of the connection terminals fitted into the contacts.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Masaoki MIYAKOSHI
  • Patent number: 10699994
    Abstract: In a semiconductor device, protective films are formed on facing side surfaces of a plurality of circuit patterns and a plating process or the like is not performed on parts aside from the side surfaces where the protective films are formed. This means that when semiconductor elements and contact elements are directly bonded via solder onto the plurality of circuit patterns, a drop-in wettability of the plurality of circuit patterns for the solder is avoided.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 30, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi Kai, Rikihiro Maruyama
  • Publication number: 20200194392
    Abstract: A semiconductor device includes: a multilayer substrate which includes a circuit board and an insulating plate on which the circuit board is formed; and a contact part having a cylindrical hollow hole therein and an open end bonded to a bonding area on the front surface of the circuit board via bonding material. In the case of this semiconductor device, wettability of a contact area of the contact part with respect to the bonding material is approximately equal to wettability of at least the bonding area of the circuit board with respect to the bonding material. Thus, the rising of the bonding material into the hollow hole of the contact part during heating performed when the contact part is bonded to the circuit board is reduced.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Masaoki MIYAKOSHI, Masayuki SOUTOME, Kazuya ADACHI, Takeshi YOKOYAMA
  • Publication number: 20200135691
    Abstract: A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Kenshi KAI, Kazuya ADACHI
  • Publication number: 20200098717
    Abstract: A conductive plate has a front surface at a front side and a rear surface at a rear side. The front surface includes a first front surface on which a first arrangement region is disposed and a second front surface on which a second arrangement region is disposed. The first front surface has a height measured from the rear surface that is different from a height of the second front surface measured from the rear surface. Next, first and second bonding materials are respectively applied to the first and second arrangement regions. A first part is bonded to the first arrangement region via the first bonding material, and a second part is bonded to the second arrangement region via the second bonding material. The heights of the first and second arrangement regions set on the front surface on the conductive plate are different from each other.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 26, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi KAI, Rikihiro MARUYAMA