Abstract: An approach for utilizing fuel gas to purge a dormant fuel gas circuit is disclosed. In one aspect, there is a fuel gas supply that supplies fuel to fuel gas circuits. Gas control valves, each coupled to one of the fuel gas circuits control the flow of fuel gas thereto from the fuel gas supply. A fuel purge system selectively purges fuel gas circuits from the fuel gas circuits that are dormant with fuel gas from the fuel gas supply.

Abstract: The invention provides a method and system for determining fluid levels in an inkjet printer. A non-contact sensor array is provided external to the container in which the levels are to be determined and each sensor in the array is sequentially switched into a sensing circuit until a change in capacitance is noted. The sensing circuit is preferably a frequency oscillation circuit whose frequency is defined by circuit capacitance.

Abstract: A downhole circulating valve includes a generally tubular outer housing having a generally axially extending internal passageway. At least one generally longitudinally extending circulating passageway is formed through at least a portion of the housing. At least one exterior port and at least one interior port are in fluid communication with the circulating passageway. At least one seal plug is disposed within the circulating passageway. The seal plug has a first position relative to the housing wherein the seal plug is remote from the exterior port and the interior port, thereby allowing fluid flow between the exterior port and the interior port through the circulating passageway. The seal plug has a second position relative to the housing wherein the seal plug is between the exterior port and the interior port and wherein the seal plug forms at least one metal-to-metal seal with the circulating passageway, thereby preventing fluid flow between the exterior port and the interior port.

Abstract: A downhole circulating valve includes a generally tubular outer housing having a generally axially extending internal passageway. At least one generally longitudinally extending circulating passageway is formed through at least a portion of the housing. At least one exterior port and at least one interior port are in fluid communication with the circulating passageway. At least one seal plug is disposed within the circulating passageway. The seal plug has a first position relative to the housing wherein the seal plug is remote from the exterior port and the interior port, thereby allowing fluid flow between the exterior port and the interior port through the circulating passageway. The seal plug has a second position relative to the housing wherein the seal plug is between the exterior port and the interior port and wherein the seal plug forms at least one metal-to-metal seal with the circulating passageway, thereby preventing fluid flow between the exterior port and the interior port.

Abstract: Systems and method for embedded trace macrocell (ETM) devices configured to dynamically interleave architecture/program tracing with microarchitecture/hardware tracing. An ETM device includes logic to enable interleaved program tracing and hardware state sampling. A core interface is configured to receive program trace and hardware state information of a microprocessor and a combining module is configured to interleave the program trace and hardware state information. A packet generation module may be configured to packetize the program trace and hardware state information into packets at operational speeds of the microprocessor.

Abstract: Described embodiments relate to methods, systems and infrastructure for flow manipulation within a porous volume. Some embodiments relate to a method of subsurface flow manipulation, comprising: providing fluid at a first subsurface location adjacent to or in a subsurface volume through which the fluid is to pass; providing first suction at a second subsurface location adjacent to or in the subsurface volume to extract fluid from the subsurface volume, the second subsurface location being located across at least part of the subsurface volume from the first subsurface location; providing fluid at a third subsurface location spaced from the first subsurface location and adjacent to or in the subsurface volume; and providing second suction at the first, second or a fourth subsurface location adjacent to the subsurface volume to extract fluid from the subsurface volume.

Abstract: A method and apparatus for shutting down a generator to prepare the generator for restart is disclosed. A power down sequence of a gas turbine of the generator is initiated from an operating state. A purge gas is forced into the gas turbine to extinguish a combustion flame in the gas turbine. The purge gas is swept through the gas turbine to displace the fuel from the gas turbine using a coast down airflow through the gas turbine during the power down sequence to prepare the generator for restart.

Abstract: A system and method of managing a stack shared by multiple threads of a processor includes allocating a first portion of a shared stack to a first thread and allocating a second portion of the shared stack to a second thread.

Abstract: A method for operating an energy system includes calculating an auto-ignition temperature of a fuel in use with the energy system, storing the auto-ignition temperature in a system memory, unloading a gas turbine associated with the energy system to a pre-determined range of operations, controlling a temperature of the exhaust flow discharged from the gas turbine, opening an exhaust bypass damper to a pre-determined position to enable a pre-determined volume of air to enter an exhaust flow path defined within the energy system, and releasing the energy system for normal operation after a pre-determined amount of time has elapsed.

Abstract: The invention provides a power-up/shut-down facility for a continuous inkjet printer which enables the printer to be readied for printing and returned to standby by operation of a single control.

Abstract: This invention relates generally to quinoline-based modulators of Liver X receptors (LXRs) and related methods.

Abstract: A method for operating an energy system includes calculating an auto-ignition temperature of a fuel in use with the energy system, storing the auto-ignition temperature in a system memory, unloading a gas turbine associated with the energy system to a pre-determined range of operations, controlling a temperature of the exhaust flow discharged from the gas turbine, opening an exhaust bypass damper to a pre-determined position to enable a pre-determined volume of air to enter an exhaust flow path defined within the energy system, and releasing the energy system for normal operation after a pre-determined amount of time has elapsed.

Abstract: A system includes a mechanism to detect addition of a memory module. In response to the addition of the memory module, a memory test is run to test the new memory module for a defect. If an uncorrectable error is detected, a routine is activated to process the error. Depending on whether the defect occurred in the new memory module or existing memory module(s), different processing is performed.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: Methods and apparatus for encoding information regarding a hardware loop of a set of packets is provided, each packet (400) containing instructions. The information is encoded into one or more bits of at least one instruction (300) in the set of packets. The information may indicate whether a packet is or is not an end packet of the loop. Information regarding two hardware loops may be encoded where information regarding the first loop is encoded into an instruction at a first position in each packet and information regarding the second loop is encoded into an instruction at a second position in each packet. End instruction information may be encoded into an instruction not having encoded loop information at the same bit positions reserved for the encoded loop information, the end instruction information indicating whether an instruction is the last instruction of a packet and the length of a packet.

Abstract: Apparatus and method for efficiently arranging and searching data in a memory space, such as a cache memory of a data storage array controller. A data structure comprises a skip list of nodes having an array of forward pointers. Each node has a node level derived from an index at which the node is stored in a table in the memory space. The total available number of nodes is preferably selected to be less than half of the largest power of 2 that can be expressed by a number of bits of the index, and the nodes are preferably stored at only even or only odd indices of the table. In such case, a free list of nodes is preferably generated from an array of pairs of counts and indices to identify the available nodes. Additional table structures can further be provided to enhance data arrangement and searching functions.

Abstract: An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

Abstract: Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

Abstract: Method and apparatus for detecting and correcting parametric failure trends in a data storage array. A plurality of data storage devices, such as hard disc drives, are arranged to form a multi-device addressable memory array space. A controller controls access to the array space, and is configured to accumulate operational performance data from each of the devices into a history log. A statistical analysis engine of the controller analyzes the data to detect anomalous operation of the devices, including a horizontal analysis of data across multiple devices. The controller initiates a data storage device specific corrective action event in response to the analysis, as required. The analysis by the engine can be in addition to, or in lieu of, analysis by the individual devices. A data request block requests additional data samples for a given parameter, or requests additional parametric data to further the analysis.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.