Abstract: A controller interconnect structure within a RAID disk array enables continuous low latency/high bandwidth communications between a plurality of controller pairs within the array. Mirror buses carry high speed mirror traffic between mirrored controllers performing mirrored memory operations. Loop buses carry inter-processor communications and other traffic between controller pairs coupled together in a controller loop. Benefits of the interconnect structure include an ability to support continued controller communications and online disk array operations under various failure and repair conditions that might otherwise render a disk array inoperable. In addition, the controller interconnect structure provides for easy expansion of the number of controllers within disk arrays as arrays continue to be scaled up in size to meet increasing storage demands from user host systems.

Abstract: A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The information is saved in memory accessible to a second processor. The information is accessed by the second processor.

Abstract: Methods and apparatus for preventing the accidental or premature decoupling of a device from a support chassis. The apparatus includes a moveable securing member. The moveable securing member is configured to be moved from a first position to a second position, wherein one of the first and second positions permits removal of the device from the support chassis, while the other position prevents removal of the device. An actuator coupled to the moveable securing member is responsive to an authorization command, so that a user or a controller can cause the securing member to be moved. The controller can be configured to operate in response to either or both of a user input or an error detection signal corresponding to the device.

Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: A verification system for an interchangeable component configured to be mated with a receiving system. The system includes a key device supported by the interchangeable component. The key device includes a transmitter configured to transmit a signal comprising component identification characteristics. The system further includes a lock system having a signal receiver and a verification component. The signal receiver is configured to receive the signal from the key device transmitter and pass the signal to the verification component. The verification component is configured to use the signal to determine whether or not the component should be admitted to the receiving system, and to generate an authorization signal if the component should be admitted.

Abstract: Methods, systems, apparatuses, and arrangements enable an identifier module of a storage system to be rendered unusable upon removal from the storage system. In an exemplary identifier module implementation, the identifier module includes an identifier data space that is capable of receiving an identifier and a breakable apparatus that is adapted to break and render the identifier module unusable upon removal of the identifier module from a storage system. The identifier module may be adapted for removable attachment to the storage system. In an exemplary storage system implementation, the storage system includes one or more memory units that are capable of storing information and at least one interface that is adapted to receive an identifier module. The at least one interface includes a disrupter apparatus that is adapted to break and render unusable an identifier module upon removal of such an identifier module from the at least one interface.

Abstract: The system and methods described herein relate to testing and verifying the fault tolerance in fault tolerant systems. Fault logic integrated into a fault tolerant system permits automated testing of fault paths in system firmware and hardware dedicated to handling fault scenarios. Advantages of the disclosed system and methods include the ability to inject errors without the need to modify system firmware or hardware. Errors can be injected in a controlled manner and asynchronously to normal system firmware execution which permits improved coverage of firmware error paths. The automated error injection capability disclosed is applicable in both the development and production of fault tolerant systems.

Abstract: A controller interconnect structure within a RAID disk array enables continuous low latency/high bandwidth communications between a plurality of controller pairs within the array. Mirror buses carry high speed mirror traffic between mirrored controllers performing mirrored memory operations. Loop buses carry inter-processor communications and other traffic between controller pairs coupled together in a controller loop. Benefits of the interconnect structure include an ability to support continued controller communications and online disk array operations under various failure and repair conditions that might otherwise render a disk array inoperable. In addition, the controller interconnect structure provides for easy expansion of the number of controllers within disk arrays as arrays continue to be scaled up in size to meet increasing storage demands from user host systems.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The information is saved in memory accessible to a second processor. The information is accessed by the second processor.

Abstract: A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The information is saved in memory accessible to a second processor. The information is accessed by the second processor.

Abstract: A method and apparatus for monitoring the movement of an object traversing a circuit and outputting data with respect thereto. Lap events are recorded and used to calculate a total lap count, split time, and elapsed time for an event that includes the repetitive traversing of a circuit. Physiologic data is monitored in the case where the object is a person. A transponder or transmitter is affixed to a user and a signal having limited range is coupled to a communications and display device when the user comes into range of the device. Each such coupling is accumulated as lap event data. Calculations are made to display the lap count and timing information as well as physiologic data. In one embodiment, the device is implemented in a watertight housing and placed at the bottom of a swimming pool. The displayed information is visible to a swimmer wearing the transponder or transmitter. In another embodiment, the display is incorporated into eyewear worn by the person traversing a repetitive circuit.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: Methods and apparatus for preventing the accidental or premature decoupling of an electrical connection, the electrical connection having two electrical connectors which can be coupled and decoupled. The invention includes a securing apparatus configured to secure the coupling of a first electrical connector to a compatible second electrical connector. The apparatus includes a moveable securing member. The moveable securing member is configured to be moved from a first position which prevents the first and second electrical connectors from being decoupled, to a second position which allows the first and second electrical connectors to be decoupled. The apparatus further includes an actuator configured to move the securing member between the first and second positions. The actuator is responsive to an authorization command, so that a user or a controller can cause the securing member to be moved. The securing apparatus can be further provided with a securing member sensor.

Abstract: A controller is presented comprising one or more initiators coupled to one or more targets via a transaction bus and a corresponding number of data busses. The initiator(s) receive transaction requests from external logic, buffer the transaction and assign it a unique identifier, which is passed to an appropriate target via the transaction bus. The targets receive and queue the unique identifier until it can process the transaction, at which time it prompts the initiator to provide it the buffered transaction via a data bus dedicated to the target.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.

Abstract: Methods and apparatus for preventing the accidental or premature decoupling of an electrical connection, the electrical connection having two electrical connectors which can be coupled and decoupled. The invention includes a securing apparatus configured to secure the coupling of a first electrical connector to a compatible second electrical connector. The apparatus includes a moveable securing member. The moveable securing member is configured to be moved from a first position which prevents the first and second electrical connectors from being decoupled, to a second position which allows the first and second electrical connectors to be decoupled. The apparatus further includes an actuator configured to move the securing member between the first and second positions. The actuator is responsive to an authorization command, so that a user or a controller can cause the securing member to be moved. The securing apparatus can be further provided with a securing member sensor.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and an operation logic. Information needed by the operation logic to perform an operation is stored in a task description block in memory by the microprocessor, and a pointer to the task description block is added to a task description block queue. The operation logic is then able to access task description blocks, based on the pointers in the queue, at will and perform the corresponding operations.