Abstract: A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure.

Abstract: A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure.

Abstract: A method can include depositing a thin metal film on a substrate of a sample, establishing a metal island on the substrate by patterning the thin metal film, and annealing the sample to de-wet the metal island and form a metal droplet from the metal island. The method can also include growing a nanowire on the substrate using the metal droplet as a catalyst, depositing a thin film of a semiconductor material on the sample, annealing the sample to allow for lateral crystallization to form a crystal grain, and patterning the crystal grain to establish a crystal island. An electronic device can be fabricated using the crystal island.

Abstract: A first side has a first surface on which is located a material, at least a portion of which is to be formed into at least one tip. A second side has a second surface which is heated. At least one of the first and second surfaces being moved so material located on the first surface comes into physical contact with the second surface. Then at least one of the first side and the second side are moved, wherein the physical contact between the material and the second surface is maintained, causing the material to stretch between the second surface and the first surface, generating at least one capillary bridge. Movement is continued until the physical contact between the material and the second surface is broken resulting in the formation of at least one sharp conductive tip.

Abstract: A first side has a first surface on which is located a material, at least a portion of which is to be formed into at least one tip. A second side has a second surface which is heated. At least one of the first and second surfaces being moved so material located on the first surface comes into physical contact with the second surface. Then at least one of the first side and the second side are moved, wherein the physical contact between the material and the second surface is maintained, causing the material to stretch between the second surface and the first surface, generating at least one capillary bridge. Movement is continued until the physical contact between the material and the second surface is broken resulting in the formation of at least one sharp conductive tip.

Abstract: A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.

Abstract: A compact, optical measurement system has a non-flat detector array having multiple detector elements arranged on a flexible substrate in a monolithic fashion, one or more illumination sources arranged to provide more than one angle of incidence of light on a subject being measured, and a detection system in electrical communication with the detector array, the detection system arranged to receive inputs from the detector array and provide a measurement from the inputs. A method of measuring reflectance of a surface includes placing the surface adjacent a hemispherical detector array, illuminating the surface from a predetermined angle of incidence, simultaneously detecting reflectance at multiple emission angles using the hemispherical detector array, and repeating the illuminating and detecting processes at different angles of incidence. Optional arrays of lenses, baffles and filters may be employed by the system.

Abstract: Embodiments pertain to a novel imaging member, namely, an electrostatic latent image generating member, and methods for using the same, that can generate an electrostatic latent image digitally with fewer steps and without using a raster output scanner (ROS) or free charge carriers. Embodiments provide a novel way of generating an electrostatic latent image without the shortfalls suffered by current photoreceptors, such as for example, charge mobility issues, unstable cycling, surface wear, lateral charge migration and sensitivity to light shock.

Abstract: A luminescent solar concentrator including a light-guiding slab containing a luminescent material that generates light emissions in response to received sunlight, spaced-apart outcoupling structures that provide a distributed outcoupling of the light emissions through predetermined locations on one of the “broadside” (e.g., upper or lower) surfaces of the light-guiding slab, and optical elements positioned to redirect the outcoupled light emissions such that the light emissions are concentrated onto a predetermined target (e.g., a PV cell). Each optical element includes a collimating surface portion and optional returner surface.

Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.

Abstract: A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: A method is provided for creating a foundational instructional design model for shareable content object (SCO) by pre-defining a semantically structured reusable learning type (RLT), and joining individual or repeated RLT's with sequence or choice indicators to form an instructional design model. The instructional design model is itself a semantically structured document that can be used and reused to create SCOs.

Abstract: An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

Abstract: A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: Embodiments pertain to a novel imaging member, namely, an electrostatic latent image generating member, and methods for using the same, that can generate an electrostatic latent image digitally with fewer steps and without using a raster output scanner (ROS) or free charge carriers. Embodiments provide a novel way of generating an electrostatic latent image without the shortfalls suffered by current photoreceptors, such as for example, charge mobility issues, unstable cycling, surface wear, lateral charge migration and sensitivity to light shock.

Abstract: A device has a substrate, a piezo polymer layer arranged adjacent the substrate, a first electrode in contact with a first side of the layer, and a second electrode arranged adjacent the first electrode, such that when the piezo layer flexes, the first and second electrodes are arranged to detect one of a change in voltage or resistance, wherein at least one of the piezo polymer layer or the electrodes are deposited by printing. A method including depositing a spacer layer onto a substrate, depositing a piezo polymer layer onto the substrate, patterning an array of first electrodes in contact with the piezo polymer layer, and patterning an array of second electrodes adjacent the array of first electrodes, wherein depositing includes one of printing and laminating and pattering includes one of printing and etching.

Abstract: A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact.