Abstract: A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property.

Abstract: A semiconductor package has first and second semiconductor die mounted to a substrate. The first semiconductor die includes a first inductor coil electrically coupled to the substrate. The second semiconductor die is mounted over the first semiconductor die. The second semiconductor die includes a second inductor coil electrically coupled to the substrate. A center of the second inductor coil has a vertical and lateral separation with respect to a center of the first inductor coil which are each selectable to minimize mutual inductive coupling between the first and second inductor coils. A spacer is disposed between the first and second semiconductor die to adjust the vertical separation. The center of the second inductor is positioned laterally within the second semiconductor die with respect to the center of the first inductor to adjust the lateral separation. The mutual inductive coupling decreases with increasing vertical and lateral separation.

Abstract: A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point.

Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract: A semiconductor die has an RF coupler and balun integrated on a common substrate. The RF coupler includes first and second conductive traces formed in close proximity. The RF coupler further includes a resistor. The balun includes a primary coil and two secondary coils. A first capacitor is coupled between first and second terminals of the semiconductor die. A second capacitor is coupled between a third terminal of the semiconductor die and a ground terminal. A third capacitor is coupled between a fourth terminal of the semiconductor die and the ground terminal. A fourth capacitor is coupled between the high side and low side of the primary coil. The integration of the RF coupler and balun on the common substrate offers flexible coupling strength and signal directivity, and further improves electrical performance due to short lead lengths, reduces form factor, and increases manufacturing yield.

Abstract: A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point.

Abstract: A method of manufacturing a semiconductor device involves providing a substrate, forming a first passivation layer over the substrate, and forming an integrated passive circuit over the substrate. The integrated passive circuit can include inductors, capacitors, and resistors. A second passivation layer is formed over the integrated passive circuit. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive circuit. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive circuit. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract: A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point.

Abstract: A semiconductor device has an inductor and capacitor formed on the substrate. The inductor and capacitor are electrically connected in series. The inductor is a coiled conductive layer. The capacitor has first and second conductive layers separated by an insulating layer. A first test pad and second test pad are formed on the substrate. A terminal of the inductor is coupled to the first and second test pads. A third test pad and fourth test pad are formed on the substrate. A terminal of the capacitor is coupled to the third and fourth test pads such that the inductor and capacitor are connected in shunt between the first and second test pads and the third and fourth test pads. An electrical characteristic of the inductor and capacitor such that resonant frequency and quality factor are tested using a two-port shunt measurement which negates series resistance of test probes.

Abstract: A semiconductor package has first and second semiconductor die mounted to a substrate. The first semiconductor die includes a first inductor coil electrically coupled to the substrate. The second semiconductor die is mounted over the first semiconductor die. The second semiconductor die includes a second inductor coil electrically coupled to the substrate. A center of the second inductor coil has a vertical and lateral separation with respect to a center of the first inductor coil which are each selectable to minimize mutual inductive coupling between the first and second inductor coils. A spacer is disposed between the first and second semiconductor die to adjust the vertical separation. The center of the second inductor is positioned laterally within the second semiconductor die with respect to the center of the first inductor to adjust the lateral separation. The mutual inductive coupling decreases with increasing vertical and lateral separation.

Abstract: A method of manufacturing a semiconductor device involves providing a substrate, forming a first passivation layer over the substrate, and forming an integrated passive circuit over the substrate. The integrated passive circuit can include inductors, capacitors, and resistors. A second passivation layer is formed over the integrated passive circuit. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive circuit. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive circuit. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

Abstract: The instant invention is an aqueous non-ionic hydrophilic polyurethane dispersion, and a continuous process for making the same. The aqueous non-ionic hydrophilic polyurethane dispersion according to instant invention includes the reaction product of a non-ionic hydrophilic prepolymer, water, optionally an external surfactant, and optionally a chain-extending reagent. The non-ionic hydrophilic prepolymer includes the reaction product of a first component and a second component. The first component is selected from the group consisting of an aromatic polyisocyanate, an aliphatic polyisocyanate, and combinations thereof. The second component is a hydrophilic alkylene oxide polyol, a non-ionic hydrophilic alkylene oxide monol, or combinations thereof.

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.

Abstract: A voltage controlled oscillator including a first oscillator circuit portion with at least one first inductor, and a second oscillator circuit portion with at least one second inductor, wherein the at least one first inductor and the at least one second inductor are electromagnetically coupled to each other.

Abstract: A voltage controlled oscillator including a first oscillator circuit portion with at least one first inductor, and a second oscillator circuit portion with at least one second inductor, wherein the at least one first inductor and the at least one second inductor are electromagnetically coupled to each other.

Abstract: In accordance with the invention, a multichip circuit is fabricated by providing an active semiconductor substrate comprising a set of isolated components including active components such as transistors, forming on a surface of the substrate a plurality of paths incorporating components from the substrate for interconnecting a plurality integrated circuit devices, and mounting the ICs on the surface in contact with their respectively appropriate paths. The preferred active substrate is similar in structure to a silicon integrated circuit except that the circuit components are interconnected only by the paths interconnecting the ICs. Advantageously the ICs are surface mounted on the substrate.

Abstract: A given testing substrate for fast-testing many integrated-circuit electronic devices, one after the other, has a set of mutually insulated collated wiring areas that can be aligned with solder-bump I/O pads of the electronic devices. At the surface of each of the corrugated areas is located a layer that is an electrically conductive durable oxide, or that is itself durable, electrically conductive, and non-oxidizable. During testing, the solder-bump I/O pads of the electronic device being tested are aligned with and pressed against the corrugated wiring areas of the given substrate. Alternatively, the electronic devices being of the electrically programmable variety, such as EPROMs, programming voltages can be delivered to each of the devices, one after the other, through the corrugated wiring areas of a single substrate.

Abstract: The present invention is predicated upon the fact that an emission trace from a plasma glow used in fabricating integrated circuits contains information about phenoma which cause variations in the fabrication process such as age of the plasma reactor, densities of the wafers exposed to the plasma, chemistry of the plasma, and concentration of the remaining material. In accordance with the present invention, a method for using neural networks to determine plasma etch end-point times in an integrated circuit fabrication process is disclosed. The end-point time is based on in-situ monitoring of the optical emission trace. The back-propagation method is used to train the network. More generally, a neural network can be used to regulate control variables and materials in a manufacturing process to yield an output product with desired quality attributes. An identified process signature which reflects the relation between the quality attribute and the process may be used to train the neural network.

Abstract: A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled.