Abstract: The use of neural networks has been employed to adjust processing during the fabrication of articles. For example, in the production of photolithographic masks by electron beam irradiation of a mask blank in a desired pattern, electrons scattered from the mask substrate cause distortion of the pattern. Adjustment for such scattering is possible during the manufacturing process by employing an adjustment function determined by a neural network whose parameters are established relative to a prototypical mask pattern.

Abstract: In wafer-scale-integrated assemblies, microminiature transmission lines are utilized as interconnects on the wafer. The extremely small cross-sectional area of a typical such line results in its total line resistance being relatively large. Such a line exhibits signal reflections and resonances. In practice, it is not feasible to eliminate these effects by conventional load termination techniques. As a result, the frequency at which digital signals can be transmitted over such a line is typically limited to well below its so-called resonance limit. In accordance with a feature of the invention, the structural parameters of each line are selected to meet specified design criteria that ensure optimal high-frequency performance of the line.

Abstract: Dielectrically isolated single crystal silicon of high quality is produced by an extremely convenient process. This process involves the fusing of two silicon bodies where at least one of these bodies has a region of silicon oxide. The bodies are contacted so that the silicon oxide is at an interface between the two bodies. The bodies are then heated to an elevated temperature while applying a nominal electrical potential across the interface. This combination of applied potential and temperature permanently fuses the two bodies without producing any significant damage to the crystal quality of these bodies.

Abstract: Dielectrically isolated areas of single crystalline silicon suitable for use in device applications have been produced utilizing a particular processing sequence. This sequence first involves producing an area of porous silicon on a silicon substrate. A single crystal region of silicon is then formed on the porous silicon through procedures such as molecular beam epitaxy, chemical vapor deposition or laser fusion. The region of the porous silicon under the single crystal silicon is then oxidized in a specifically controlled manner to form an insulator.

Abstract: Automatic Process Control Device having input transistors to receive process and set point signals; a subtractive amplifier to compare the process and set point signals and produce one of two amplified deviation signals which are limited to maximum values by zener diodes; capacitors to receive, time-integrate and store the amplified and limited deviation signals, and produce a neutral output if the time-integration of the amplified and limited deviation signals is in balance, and one of two trigger signals if the time-integration of the amplified and limited deviation signals is positive or negative; and relay switches connected to discharging circuits and in series with zener diodes to receive the trigger signals and operate a controlling device upon the process to urge the process toward its desired set point, and simultaneously produce a corresponding tripping signal which urges the capacitors toward a status to produce the neutral output, such that as the controlling device is operating upon the process t

Abstract: Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

Abstract: Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

Abstract: Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

Abstract: Process for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.