Abstract: A method and apparatus for predicting a reference voltage in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller includes a lookup table having a number of different reference voltage values each corresponding to one of a number of different performance states. The memory controller further includes calibration circuitry configured to determine reference voltages for operation in various performance states. Responsive to returning to a performance state after operating in another, the calibration circuitry may restore the reference voltage to its most recently used value, and also obtain a predicted reference voltage. Calibrations may be performed at both the restored reference voltage and the predicted reference voltage obtained from the lookup table. The subsequent operating reference voltage may then be selected based on which of the two calibrations resulted in the largest data eye width.

Abstract: A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.

Abstract: A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.

Abstract: A method and apparatus for predicting a reference voltage in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller includes a lookup table having a number of different reference voltage values each corresponding to one of a number of different performance states. The memory controller further includes calibration circuitry configured to determine reference voltages for operation in various performance states. Responsive to returning to a performance state after operating in another, the calibration circuitry may restore the reference voltage to its most recently used value, and also obtain a predicted reference voltage. Calibrations may be performed at both the restored reference voltage and the predicted reference voltage obtained from the lookup table. The subsequent operating reference voltage may then be selected based on which of the two calibrations resulted in the largest data eye width.

Abstract: A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller is coupled to receive data during reads from the memory on a functional data path and a duplicate data path. The memory controller further includes calibration circuitry. During reads of data conducted during normal operation, the calibration circuit calibrates a first delay locked loop (DLL) in the duplicate data path. A second DLL, in the functional data path, may be adjusted based on the calibrations conducted in the duplicate data path.

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Abstract: Systems, methods, and devices are provided for generating a tone mapping function used in adjusting the power consumed by a backlight of an electronic display. One such method includes sampling an image frame in framebuffer space and generating a tone mapping function in linear space. The tone mapping function may have at least two portions: a nondistorting portion that does not to distort pixels to which it applies when an intensity of a backlight of the electronic display is modified and a distorting portion that does distort pixels to which it applies when the intensity of the backlight is modified. Thereafter, the intensity of the backlight may be modified based at least in part on the nondistorting portion of the tone mapping function, the tone mapping function converted to framebuffer space, and the tone mapping function applied to the image frame or a subsequent image frame.

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

Abstract: A method and apparatus for adaptive calibration scheduling is disclosed. A calibration circuit may perform calibrations of a delay applied to a data strobe conveyed from a memory controller to the memory, and may also calibrate a reference voltage. After calibrating the data strobe delay, a current width of an eye opening and a current score are determined. If the eye opening is not less than a minimum threshold and the current score is within a specified range of a reference score, the reference voltage calibration, if conditionally scheduled, is inhibited. The results of the calibration may be recorded in a history table. A timer may advance a pointer provided to a sequence table at a rate determined by information stored in the history table. Information stored in an entry of the sequence table may indicate which calibration procedures are to be performed during the next calibration cycle.

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Abstract: A method and apparatus for using neighboring sampling points in a memory subsystem calibration is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto. A calibration unit in the memory controller is configured to perform calibrations of a data strobe signal and a reference voltage to determine eye openings for signals conveyed between the memory and the memory controller. Performing the calibration includes determining a number of different calibration points and computing initial scores for each of the calibration points. The method further includes calculating adjusted scores for each calibration point. For a given calibration point, the adjusted score includes weighted values of one or more calibration points that are adjacent thereto. The method further includes selecting a calibration point having the highest adjusted score as the calibrated value.

Abstract: A system and method for calibrating memory using credit-based segmentation control is disclosed. A memory and a memory controller coupled thereto. The memory controller includes a calibration circuit configured to calibrate a data strobe signal conveyed to/from the memory. The calibration may be subdivided, in time, into a number of segments. The memory controller also includes a credit circuit configured to provide a condition code to the calibration circuit. The condition code may be indicative of an amount of time a request has been pending, or how many request are pending. If the condition code indicates that a request has been pending for more than a certain amount of time, the calibration may be terminated.

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

Abstract: A system and method for calibrating memory using credit-based segmentation control is disclosed. A memory and a memory controller coupled thereto. The memory controller includes a calibration circuit configured to calibrate a data strobe signal conveyed to/from the memory. The calibration may be subdivided, in time, into a number of segments. The memory controller also includes a credit circuit configured to provide a condition code to the calibration circuit. The condition code may be indicative of an amount of time a request has been pending, or how many request are pending. If to the condition code indicates that a request has been pending for more than a certain amount of time, the calibration may be terminated.

Abstract: A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract: Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).

Abstract: In some embodiments, a memory interface system includes a memory interface circuit and a memory controller. The memory interface circuit is configured to communicate with a memory device. The memory controller is configured, in response to the memory device operating at a first frequency, to store configuration information corresponding to the memory device operating at a second frequency. The memory controller is further configured, in response to the memory device transitioning to the second frequency, to send the configuration information to the memory interface circuit. In some embodiments, storing the configuration information may result in some memory requests being provided to the memory device more quickly, as compared to a different memory interface system where the configuration information is not stored at the memory controller.

Abstract: An apparatus and method for a restricted range calibration is disclosed. A system includes a memory coupled to a memory controller. The memory controller is coupled to receive a clock signal, and is configured to operate in different performance states corresponding to different frequencies of the clock signal. The memory controller provides a data strobe signal to synchronize transfers of data to and from the memory. When operating in a first performance state, the memory controller may perform a first calibration of a delay applied to the data strobe signal. Performing the first calibration includes varying the delay over a first range of values. Thereafter, responsive to returning to the first performance state from another performance state, the memory controller may perform a second calibration. The second calibration includes varying the delay over a second range of values that is less than the first range.

Abstract: A method and apparatus for memory subsystem calibration in which periodic calibrations of a data strobe delay and reference voltage are scheduled. After a first calibration, a reference score is determined based on a parameter of an eye opening. On a next scheduled calibration thereafter, the data strobe delay is calibrated at the most recent value of the reference voltage. A score is then determined, and compared to the reference score. If the score is within a specified range of the reference score, then no calibration of the reference voltage is performed on the current cycle. Otherwise, the reference voltage is calibrated as well.