Abstract: A method and apparatus for memory calibration averaging is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller. The memory controller includes a calibration control circuit that periodically performs calibrations of the memory subsystem. Calibration may be performed for a delay applied to a data strobe used to synchronized transfers of data between the memory controller and the memory, and a reference voltage used to distinguish between a logic 0 and a logic 1 during memory reads. Following the performance of a calibration, the values of the delay and the reference voltage may be set based on an average of a most recent number of calibrations.

Abstract: A method and apparatus for pre-calibration of various system performance states is disclosed. In one embodiment, a method includes, for each of a number of different performance states (or operating points), performing initial calibrations of various parameters associated with transfers of data between a memory and a memory controller. After completing the initial calibrations, the calibrated values are stored. Thereafter, during normal operation and following a change to a new performance state, the values of the various parameters are set to the values to which they were calibrated during the initial calibration for that state.

Abstract: In some embodiments, a memory interface system includes a memory interface circuit and a memory controller. The memory interface circuit is configured to communicate with a memory device. The memory controller is configured, in response to the memory device operating at a first frequency, to store configuration information corresponding to the memory device operating at a second frequency. The memory controller is further configured, in response to the memory device transitioning to the second frequency, to send the configuration information to the memory interface circuit. In some embodiments, storing the configuration information may result in some memory requests being provided to the memory device more quickly, as compared to a different memory interface system where the configuration information is not stored at the memory controller.

Abstract: A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments.

Abstract: A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.

Abstract: A method and apparatus for conditional cancellation of a calibration procedure is performed. In one embodiment, a memory controller is coupled to memory. The memory controller is configured to convey data and a data strobe signal to the memory. The memory controller may conduct calibrations of a delay of the data strobe signal to ensure sufficient setup and hold time for the data. After an initial calibration, and at each of a number of periodic intervals, the memory controller may determine whether one or more parameters is within a specified range. If one of the one or more parameters is not within its respective specified range, another calibration of the data strobe delay may be performed. However, if each of the one or more parameters is within its respective specified range, the calibration may be canceled.

Abstract: Systems, methods, and devices are provided for temporal filtering of tone mapping slopes used in adjusting the power consumed by a backlight of an electronic display. One such method involves computing a current first target slope of an intermediate tone mapping function based at least in part on characteristics of a current image frame and temporally filtering the current first target slope to obtain a current first transition slope. A current backlight intensity of the display and a current final tone mapping function may be determined based at least in part on the current first transition slope. The current final tone mapping function may be applied to the current image frame or a subsequent image frame.

Abstract: A method and apparatus for performing a data strobe-to-data delay calibration is disclosed. In one embodiment, a data strobe signal, along with data, is conveyed from a memory controller to a memory. An initial delay calibration procedure may be performed to align the data and the data strobe signals at the memory, with subsequent calibrations performed there between in order to compensate for changes due to various factors such as voltage and temperature. In the calibrations performed between the delay calibration procedures, a calibrated delay value may be multiplied by a first scaling factor and a second scaling factor to generate a scaled code. A DLL configured to convey the data strobe signal may then be programmed based on this code.

Abstract: A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments.

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. The memory interface unit may be configured to operate in a normal mode and a low power mode. However, in response to an occurrence of a given predetermined interval while the memory interface unit is in the low power mode, the memory interface unit may be configured to calibrate the timing unit subsequent to transitioning to the normal mode.

Abstract: Systems, methods, and devices are provided for histogram generation and evaluation used in adjusting the power consumed by a backlight of an electronic display. One such method involves generating a pixel brightness histogram of an image frame passing through a pixel pipeline in a nonlinear space. One or more pixel brightness values from the histogram may be selected before being converted from the nonlinear space into a linear space. A tone mapping function and backlight intensity are determined based at least in part on the one or more pixel brightness values in the linear space. The resulting tone mapping function is converted to the nonlinear space and applied to the image frame or a subsequent image frame in the pixel pipeline. The pixels of the image frame to which the nondistorting portion of the tone mapping function is applied may appear substantially undistorted despite a reduction in backlight intensity.

Abstract: Systems, methods, and devices are provided for generating a tone mapping function used in adjusting the power consumed by a backlight of an electronic display. One such method includes sampling an image frame in framebuffer space and generating a tone mapping function in linear space. The tone mapping function may have at least two portions: a nondistorting portion that does not to distort pixels to which it applies when an intensity of a backlight of the electronic display is modified and a distorting portion that does distort pixels to which it applies when the intensity of the backlight is modified. Thereafter, the intensity of the backlight may be modified based at least in part on the nondistorting portion of the tone mapping function, the tone mapping function converted to framebuffer space, and the tone mapping function applied to the image frame or a subsequent image frame.

Abstract: Systems, methods, and devices are provided for temporal filtering of tone mapping slopes used in adjusting the power consumed by a backlight of an electronic display. One such method involves computing a current first target slope of an intermediate tone mapping function based at least in part on characteristics of a current image frame and temporally filtering the current first target slope to obtain a current first transition slope. A current backlight intensity of the display and a current final tone mapping function may be determined based at least in part on the current first transition slope. The current final tone mapping function may be applied to the current image frame or a subsequent image frame.

Abstract: Systems, methods, and devices are provided for histogram generation and evaluation used in adjusting the power consumed by a backlight of an electronic display. One such method involves generating a pixel brightness histogram of an image frame passing through a pixel pipeline in a nonlinear space. One or more pixel brightness values from the histogram may be selected before being converted from the nonlinear space into a linear space. A tone mapping function and backlight intensity are determined based at least in part on the one or more pixel brightness values in the linear space. The resulting tone mapping function is converted to the nonlinear space and applied to the image frame or a subsequent image frame in the pixel pipeline. The pixels of the image frame to which the nondistorting portion of the tone mapping function is applied may appear substantially undistorted despite a reduction in backlight intensity.

Abstract: In one embodiment, a processor is operable to issue a first memory request to access a particular memory location, and, prior to completion of the first memory request, to issue a command to release a memory lock on the particular memory location when access to the particular memory location is complete. The processor is further operable to, prior to release of the memory lock, issue a second memory request to access a different memory location. Also a memory management unit is operable to receive the command to release the memory lock and to monitor for when access to the particular memory location is complete. The memory management unit releases the memory lock in response to completion.

Abstract: A technique efficiently accesses locks associated with resources in a computer system. A processor accesses (e.g., acquires or releases) a lock by specifying and issuing a request to a resource controller, the request containing attribute and resource location information associated with the lock. In response, the resource controller applies the information contained in the request to an outstanding lock data structure to determine if the request should be blocked, blocked as a pending writer, allowed or an error condition. If the request is blocked, it remains blocked until the outstanding lock blocking the request is released. If the request is allowed, operations associated with the request are performed.

Abstract: A system and method for enabling a processor to access a memory not directly coupled to the processor. A memory request, including a request identifier field, is issued by a processor to a local memory management unit (MMU). Using the request identifier field, the local MMU determines whether the memory request should be issued by the local memory management unit (MMU) to a local memory, or should be transferred by the local MMU to a remote MMU and issued by the remote MMU to a remote memory, the remote memory associated with a different processor. In this manner, the remote MMU issues certain memory requests on behalf of the local processor and returns any results back to the local processor.