Patents by Inventor Robert H. Dennard
Robert H. Dennard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9564500Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.Type: GrantFiled: June 30, 2015Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Takashi Ando, Robert H. Dennard, Isaac Lauer, Ramachandran Muralidhar
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Publication number: 20170005090Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Takashi Ando, Robert H. Dennard, Isaac Lauer, Ramachandran Muralidhar, Ghavam G. Shahidi
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Publication number: 20170004873Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.Type: ApplicationFiled: September 15, 2016Publication date: January 5, 2017Inventors: Jin Cai, Kangguo Cheng, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning
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Publication number: 20170005173Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Takashi Ando, Robert H. Dennard, Isaac Lauer, Ramachandran Muralidhar
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Publication number: 20160365252Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Takashi Ando, Robert H. Dennard, Martin M. Frank
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Patent number: 9484464Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.Type: GrantFiled: August 25, 2014Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Kangguo Cheng, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning
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Patent number: 9466492Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.Type: GrantFiled: January 26, 2015Date of Patent: October 11, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Robert H. Dennard, Martin M. Frank
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Patent number: 9425080Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.Type: GrantFiled: January 20, 2015Date of Patent: August 23, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Robert H. Dennard, Hemanth Jagannathan, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi
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Patent number: 9379028Abstract: SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.Type: GrantFiled: November 16, 2009Date of Patent: June 28, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jin Cai, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning, Jeng-Bang Yau
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Publication number: 20150318177Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.Type: ApplicationFiled: January 26, 2015Publication date: November 5, 2015Inventors: Takashi Ando, Robert H. Dennard, Martin M. Frank
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Publication number: 20150132896Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.Type: ApplicationFiled: January 20, 2015Publication date: May 14, 2015Inventors: Kangguo Cheng, Robert H. Dennard, Hemanth Jagannathan, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi
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Patent number: 8994006Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.Type: GrantFiled: October 2, 2012Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Robert H. Dennard, Hemanth Jagannathan, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi
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Patent number: 8947927Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).Type: GrantFiled: July 30, 2009Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Wing K. Luk, Robert H. Dennard
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Patent number: 8941412Abstract: A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.Type: GrantFiled: September 6, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Wing K. Luk, Robert H. Dennard
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Publication number: 20140362638Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.Type: ApplicationFiled: August 25, 2014Publication date: December 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Kangguo Cheng, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning
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Patent number: 8877606Abstract: A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.Type: GrantFiled: January 16, 2012Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Robert H. Dennard, David R. Greenberg, Amlan Majumdar, Leathen Shi, Jeng-Bang Yau
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Patent number: 8859302Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.Type: GrantFiled: February 28, 2011Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Ali Khakifirooz, Jin Cai, Kangguo Cheng, Robert H. Dennard, Tak H. Ning
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Patent number: 8847348Abstract: An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.Type: GrantFiled: July 23, 2013Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Jin Cai, Robert H. Dennard, Wilfried E. Haensch, Tak H. Ning
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Patent number: 8815684Abstract: A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor.Type: GrantFiled: December 7, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Jin Cai, Kevin K. Chan, Robert H. Dennard, Bruce B. Doris, Barry P. Linder, Ramachandran Muralidhar, Ghavam G. Shahidi
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Patent number: 8754672Abstract: A reversible, switched capacitor voltage conversion apparatus includes a plurality of individual unit cells coupled to one another in stages, with each unit cell comprising multiple sets of inverter devices arranged in a stacked configuration, such that each set of inverter devices operates in separate voltage domains wherein outputs of inverter devices in adjacent voltage domains are capacitively coupled to one another such that a first terminal of a capacitor is coupled to an output of a first inverter device in a first voltage domain, and a second terminal of the capacitor is coupled to an output of a second inverter in a second voltage domain; and wherein, for both the first and second voltage domains, outputs of at least one of the plurality of individual unit cells serve as corresponding inputs for at least another one of the plurality of individual unit cells.Type: GrantFiled: March 14, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Brian L. Ji