Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P? closer to insulator layer).

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.

Abstract: Device structures including a silicon-controlled rectifier and methods of forming a device structure including a silicon-controlled rectifier. The device structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite from the first conductivity type. The second well adjoins the first well along an interface. A third doped region includes a first portion in the first well and a second portion in the second well, and a gate structure that overlaps with a portion of the second well.

Abstract: Embodiments of the disclosure provide a semiconductor controlled rectifier (SCR) structure and methods to form the same. The SCR structure may include a first polycrystalline semiconductor material on a first insulator and includes a first well therein. A monocrystalline semiconductor material is adjacent the first polycrystalline semiconductor material and includes an anode region and a cathode region therein. A second polycrystalline semiconductor material is on a second insulator and includes a second well therein.

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge device (ESD) with a pinch resistor and methods of manufacture. The structure includes: a semiconductor substrate; a shallow trench isolation structure extending into the semiconductor substrate; an amorphous layer in the semiconductor substrate and below the shallow trench isolation structure; and a pinch resistor between the shallow trench isolation structure and the amorphous layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

Abstract: An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P- closer to insulator layer).

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.