Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

Abstract: Silicon-controlled rectifiers, electrostatic discharge circuits, and methods of fabricating a silicon-controlled rectifier for use in an electrostatic discharge circuit. A device structure for the silicon controlled rectifier includes a first well of a first conductivity type in a semiconductor layer, a second well of a second conductivity type in the semiconductor layer, a cathode coupled with the first well, and an anode coupled with the second well. First and second body contacts are coupled with the first well, and the first and second body contacts each have the first conductivity type. A triggering device may be coupled with the first body contact.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from an electrostatic discharge event at an input/output pin. The protection circuit includes a silicon-controlled rectifier having a well and an anode in the well. The anode is coupled with the input/output pin. The protection circuit further includes a control circuit coupled with the well. The control circuit is configured to supply a first control logic voltage to the well that places the silicon-controlled rectifier in a blocking state, and a second control logic voltage to the well that places the silicon-controlled rectifier in a low impedance state. When placed in its low impedance state, the silicon-controlled rectifier is configured to divert current from the electrostatic discharge event at the input/output pin away from the integrated circuit.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: An electrostatic discharge protection circuit includes a power clamp device, a timing circuit including a first resistor, a first capacitor that is connected with the first resistor at a first node, and a second capacitor that is connected to a second node, a logic gate including a first input connected with the first node, a second input connected with the second node, and an output connected with the power clamp device, and a decoder device connected with a first address pin and a second address pin. The first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.

Abstract: An electrostatic discharge protection circuit includes a transistor device, a first timing circuit including a first resistor and a first capacitor that is connected with the first resistor at a first node, a second timing circuit including a second resistor and a second capacitor that is connected with the second resistor at a second node, and a logic gate including a first input connected with the first node, a second input coupled with the second node, and an output connected with the transistor device.

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.