Patents by Inventor Robert J. Royer, Jr.
Robert J. Royer, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220416997Abstract: Methods and apparatus relating to handling unaligned transactions for inline encryption are described. In an embodiment, cryptographic logic circuitry receives a plurality of incoming packets and store two or more incoming packets from the plurality of incoming packets in memory. The cryptographic logic circuitry is informs software in response to detection of the two or more incoming packets. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Prashant Dewan, Siddhartha Chhabra, Robert J. Royer, JR., Michael Glik, Baiju Patel
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Publication number: 20220121263Abstract: In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.Type: ApplicationFiled: December 23, 2021Publication date: April 21, 2022Inventors: Christopher P. MOZAK, Robert J. ROYER, Jr., Aaron MARTIN, Alex P. THOMAS, Tomer LEVY, Noam LUPOVICH
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Publication number: 20210325956Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Virendra Vikramsinh ADSURE, Chia-Hung S. KUO, Robert J. ROYER, JR., Deepak GANDIGA SHIVAKUMAR
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Patent number: 11042297Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.Type: GrantFiled: May 20, 2019Date of Patent: June 22, 2021Assignee: Intel CorporationInventors: Blaise Fanning, Mark A. Schmisseur, Raymond S. Tetrick, Robert J. Royer, Jr., David B. Minturn, Shane Matthews
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Patent number: 11036412Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.Type: GrantFiled: September 27, 2019Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Sahar Khalili, Zvika Greenfield, Sowmiya Jayachandran, Robert J. Royer, Jr., Dimpesh Patel
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Patent number: 10956323Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.Type: GrantFiled: May 10, 2018Date of Patent: March 23, 2021Assignee: INTEL CORPORATIONInventors: Dale J. Juenemann, James A. Boyd, Robert J. Royer, Jr.
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Patent number: 10949356Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.Type: GrantFiled: June 14, 2019Date of Patent: March 16, 2021Assignee: Intel CorporationInventors: James A. Boyd, Robert J. Royer, Jr., Lily P. Looi, Gary C. Chow, Zvika Greenfield, Chia-Hung S. Kuo, Dale J. Juenemann
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Publication number: 20200226066Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Eran SHIFER, Zeshan A. CHISHTI, Sanjay K. KUMAR, Zvika GREENFIELD, Philip LANTZ, Eshel SERLIN, Asaf RUBINSTEIN, Robert J. ROYER, JR.
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Patent number: 10649484Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.Type: GrantFiled: April 23, 2018Date of Patent: May 12, 2020Assignee: INTEL CORPORATIONInventors: Anoop Mukker, Eng Hun Ooi, Robert J. Royer, Jr., Brian R. McFarlane
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Patent number: 10572339Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 27, 2018Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Robert J. Royer, Jr., Blaise Fanning, Eng Hun Ooi
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Publication number: 20200034061Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.Type: ApplicationFiled: September 27, 2019Publication date: January 30, 2020Inventors: Sahar KHALILI, Zvika GREENFIELD, Sowmiya JAYACHANDRAN, Robert J. ROYER, JR., Dimpesh PATEL
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Patent number: 10540505Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.Type: GrantFiled: September 29, 2017Date of Patent: January 21, 2020Assignee: Intel CorporationInventors: James A. Boyd, Dale J. Juenemann, Robert J. Royer, Jr.
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Publication number: 20190339869Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.Type: ApplicationFiled: May 20, 2019Publication date: November 7, 2019Inventors: Blaise FANNING, Mark A. SCHMISSEUR, Raymond S. TETRICK, Robert J. ROYER, JR., David B. MINTURN, Shane MATTHEWS
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Publication number: 20190303300Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.Type: ApplicationFiled: June 14, 2019Publication date: October 3, 2019Inventors: James A. BOYD, Robert J. ROYER, JR., Lily P. LOOI, Gary C. CHOW, Zvika GREENFIELD, Chia-Hung S. KUO, Dale J. JUENEMANN
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Patent number: 10402565Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.Type: GrantFiled: January 30, 2017Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Nitin V. Sarangdhar, Robert J. Royer, Jr., Eng Hun Ooi, Brian R. McFarlane, Mukesh Kataria
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Patent number: 10304814Abstract: An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.Type: GrantFiled: June 30, 2017Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Konika Ganguly, Robert J. Royer, Jr., Rebecca Z. Loop, Anthony M. Constantine, Bilal Khalaf
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Patent number: 10296217Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.Type: GrantFiled: June 9, 2017Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: Blaise Fanning, Mark A. Schmisseur, Raymond S. Tetrick, Robert J. Royer, Jr., David B. Minturn, Shane Matthews
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Publication number: 20190129792Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 27, 2018Publication date: May 2, 2019Applicant: Intel CorporationInventors: Robert J. Royer, JR., Blaise Fanning, Eng Hun Ooi
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Publication number: 20190102565Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: INTEL CORPORATIONInventors: JAMES A. BOYD, DALE J. JUENEMANN, ROBERT J. ROYER, JR.
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Patent number: 10248343Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.Type: GrantFiled: November 21, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Jason B. Akers, Knut S. Grimsrud, Robert J. Royer, Jr., Richard P. Mangold, Sanjeev N. Trika